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PDF ORT4622 Data sheet ( Hoja de datos )
| Número de pieza | ORT4622 | |
| Descripción | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver | |
| Fabricantes | Agere Systems | |
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Preliminary Data Sheet
March 2000
ORCA® ORT4622 Field-Programmable System Chip (FPSC)
Four-Channel x 622 Mbits/s Backplane Transceiver
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of FPGA-based design implemen-
tation, coupled with high-speed serial backplane data
transfer. The 622 Mbits/s backplane transceiver
offers a clockless, high-speed interface for interde-
vice communication on a board or across a back-
plane. The built-in clock recovery of the ORT4622
allows for higher system performance, easier-to-
design clock domains in a multiboard system, and
fewer signals on the backplane. Network designers
will benefit from the backplane transceiver as a net-
work termination device. The backplane transceiver
offers SONET scrambling/descrambling of data and
streamlined SONET framing, pointer moving, and
transport overhead handling, plus the programmable
logic to terminate the network into proprietary sys-
tems. For non-SONET applications, all SONET func-
tionality is hidden from the user and no prior
networking knowledge is required.
Embedded Core Features
s Implemented in an ORCA Series 3 FPGA array.
s Allows wide range of applications for SONET net-
work termination application as well as generic data
moving for high-speed backplane data transfer.
s No knowledge of SONET/SDH needed in generic
applications. Simply supply data, 78 MHz clock, and
a frame pulse.
s High-speed interface (HSI) function for clock/data
recovery serial backplane data transfer without
external clocks.
Table 1. ORCA ORT4622—Available FPGA Logic
s HSI function uses Lucent Technologies Microelec-
tronics Group’s proven 622 Mbits/s serial interface
core.
s Four-channel HSI function provides 622 Mbits/s
serial interface per channel for a total chip band-
width of 2.5 Gbits/s (full duplex).
s LVDS I/Os compliant with EIA*-644, support hot
insertion.
s 8:1 data multiplexing/demultiplexing for 77.76 MHz
byte-wide data processing in FPGA logic.
s On-chip phase-lock loop (PLL) clock meets B jitter
tolerance specification of ITU-T Recommendation
G.958 (0.6 UIP-P at 250 kHz).
s Powerdown option of HSI receiver on a per-
channel basis.
s Highly efficient implementation with only 3% over-
head vs. 25% for 8B10B coding.
s In-Band management and configuration.
s Streamlined pointer processor (pointer mover) for
8 kHz frame alignment to system clocks.
s Built-in boundry scan (IEEE† 1149.1 JTAG).
s FIFOs align incoming data across all four channels
for STS-48 (2.5 Gbits/s) operation (in quad STS-12
format).
s 1 + 1 protection supports STS-12/STS-48 redun-
dancy by either software or hardware control for
protection switching applications.
* EIA is a registered trademark of Electronic Industries Associa-
tion.
† IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Device
ORT4622
Usable
System
Gates‡
60K—120K
Number of
LUTs
4032
Number of
Registers
5304
Max User
RAM
64K
Max User
I/Os
Array Size
Number of
PFUs
259 18 x 28 504
‡ The embedded core and interface are not included in the above gate counts. The usable gate count range from a logic-only gate count to
a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as
108 gates per PFU/SLIC), including 12 gates pre-LUT/FF pair (eight per PFU), and 12 gates per SLC/FF pair (one per PFU). Each of the
four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are
counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU.
1 page  
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Description
What Is an FPSC?
FPSCs, or field-programmable system chips, are
devices that combine field-programmable logic with
ASIC or mask-programmed logic on a single device.
FPSCs provide the time to market and flexibility of
FPGAs, the design effort savings of using soft intellec-
tual property (IP) cores, and the speed, design density,
and economy of ASICs.
FPSC Overview
Lucent’s Series 3+ FPSCs are created from Series 3
ORCA FPGAs. To create a Series 3+ FPSC, several
rows of programmable logic cells (see FPGA Logic
Overview section for FPGA logic details) are removed
from a Series 3 ORCA FPGA, and the area is replaced
with an embedded logic core. Other than replacing
some FPGA gates with ASIC gates, at greater than
10:1 efficiency, none of the FPGA functionality is
changed—all of the Series 3 FPGA capability is
retained: MPI, PCMs, boundary scan, etc. The rows of
programmable logic are replaced at the bottom of the
device, allowing pins on the bottom and sides of the
replaced rows to be used as I/O pins for the embedded
core. The remainder of the device pins retain their
FPGA functionality as do special function FPGA pins
within the embedded core area.
The embedded cores can take many forms and gener-
ally come from Lucent Technologies ASIC libraries.
Other offerings allow customers to supply their own
core functions for the creation of custom FPSCs.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its
embedded core (standard-cell/ASIC gates) and its
FPGA gates. Because FPGA gates are generally
expressed as a usable range with a nominal value, the
total FPSC gate count is sometimes expressed in the
same manner. Standard-cell ASIC gates are, however,
10 to 25 times more silicon area efficient than FPGA
gates. Therefore, an FPSC with an embedded function
is gate equivalent to an FPGA with a much larger gate
count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embed-
ded core is designed to look like FPGA I/Os from the
FPGA side, simplifying interface signal routing and pro-
viding a unified approach with general FPGA design.
Effectively, the FPGA is designed as if signals were
going off of the device to the embedded core, but the
on-chip interface is much faster than going off-chip and
requires less power. All of the delays for the interface
are precharacterized and accounted for in the ORCA
Foundry Development System.
Clock spines also can pass across the FPGA/embed-
ded core boundary. This allows for fast, low-skew
clocking between the FPGA and the embedded core.
Many of the special signals from the FPGA, such as
DONE and global set/reset, are also available to the
embedded core, making it possible to fully integrate the
embedded core with the FPGA as a system.
For even greater system flexibility, FPGA configuration
RAMs are available for use by the embedded core.
This allows for user-programmable options in the
embedded core, in turn allowing for greater flexibility.
Multiple embedded core configurations may be
designed into a single device with user-programmable
control over which configurations are implemented, as
well as the capability to change core functionality sim-
ply by reconfiguring the device.
ORCA Foundry Development System
The ORCA Foundry Development System is used to
process a design from a netlist to a configured FPSC.
This system is used to map a design onto the ORCA
architecture and then place and route it using ORCA
Foundry’s timing-driven tools. The development system
also includes interfaces to, and libraries for, other popu-
lar CAE tools for design entry, synthesis, simulation,
and timing analysis.
The ORCA Foundry Development System interfaces to
front-end design entry tools and provides the tools to
produce a configured FPSC. In the design flow, the
user defines the functionality of the FPGA portion of
the FPSC and embedded core settings at two points in
the design flow: at design entry and at the bit stream
generation stage. Following design entry, the develop-
ment system’s map, place, and route tools translate the
netlist into a routed FPSC. A static timing analysis tool
is provided to determine device speed, and a back-
annotated netlist can be created to allow simulation.
Lucent Technologies Inc.
Lucent Technologies Inc.
5
5 Page 
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
ORT4622 Overview (continued)
TOH CLK
TX TOH CLK EN
TOH TX A
9
TX BUS A
LINE LBPK
(SOFT CTL)
TO RX TOH PROC.
TX TOH
PROCESSOR
FRAME
PROC.
QUAD CHANNEL
TRANSMITTER
TX CH A
(MACRO)
2 LVDS
OUT A
TOH TX B
TX BUS B
9
TX TOH
PROCESSOR
FRAME
PROC.
TX CH B
(MACRO)
2 LVDS
OUT B
TOH TX C
TX BUS C
9
TX TOH
PROCESSOR
FRAME
PROC.
TX CH C
(MACRO)
2 LVDS
OUT C
TOH TX D
TX BUS D
9
SYSTEM FRAME
SYSTEM CLOCK
LINE FRAME
PROT SWITCH A/B
12
DATA RX BUS A
DATA RX A EN
12
DATA RX BUS B
DATA RX B EN
PROT SWITCH C/D
12
DATA RX BUS C
DATA RX C EN
12
DATA RX BUS D
DATA RX D EN
TOH_EN
TOH RX A
TOH RX B
TOH RX C
TOH RX D
RX TOH CLK FPEN
RX TOH CLK EN
RX TOH FRAME
SOFT CTL
SOFT CTL
SOFT CTL
SOFT CTL
SOFT CTL
SOFT CTL
TX TOH
PROCESSOR
FRAME
CLOCK
77.76
MHz
FRAME
PROC.
TX CH D
(MACRO)
77.76
MHz
622 MHz
FDBK
REF
/8
PLL
622 MHz Clks
RX CH A
77.76 (MACROCELL)
MHz
POINTER
MOVER
STS48
RX CH B
(MACROCELL)
77.76
MHz
FIFO
RX CH C
(MACROCELL)
77.76
MHz
SOFT CTL
TOH CLK
SOFT CTL
CH A
CH B
SOFT CTL
CH C
RX TOH
PROCESSOR
CH D
SOFT CTL
RX CH D
(MACROCELL)
77.76
MHz
LVDS LPBK
(SOFT CTL)
QUAD CHANNEL
RECEIVER
CPU INTERFACE (ASYNC)
8
7
2 LVDS
OUT D
SYSTEM CLOCK
(77.76 MHz)
2 LVDS
IN A
2 LVDS
IN B
2 LVDS
IN C
2 LVDS
IN D
DEVICE I/O OR FPGA I/F SIGNALS (BIT STREAM SELECTABLE)
Figure 2. Architecture of ORT4622 Backplane Transceiver
Lucent Technologies Inc.
Lucent Technologies Inc.
5-8576 (F)
11
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