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PDF ORT8850 Data sheet ( Hoja de datos )
| Número de pieza | ORT8850 | |
| Descripción | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver | |
| Fabricantes | Agere Systems | |
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Data Sheet
August 2001
ORCA® ORT8850 Field-Programmable System Chip (FPSC)
Eight-Channel x 850 Mbits/s Backplane Transceiver
Introduction
Field-programmable system chips (FPSCs) bring a
whole new dimension to programmable logic: FPGA
logic and an embedded system solution on a single
device. Agere Systems Inc. has developed a solution
for designers who need the many advantages of
FPGA-based design implementation, coupled with
high-speed serial backplane data transfer. Built on the
Series 4 reconfigurable embedded system-on-chips
(SoC) architecture, the ORT8850 family is made up of
backplane transceivers containing eight channels,
each operating at up to 850 Mbits/s (6.8 Gbits/s when
all eight channels are used) full-duplex synchronous
interface, with built-in clock and data recovery (CDR)
in standard-cell logic, along with up to 600K usable
FPGA system gates. The CDR circuitry is a macrocell
available from Agere’s Smart Silicon macro library,
and has already been implemented in numerous
applications including ASICs, standard products, and
FPSCs to create interfaces for SONET/SDH STS-3/
STM-1, STS-12/STM-4, STS-48/STM-16, and STS-
192/STM-64 applications. With the addition of protocol
and access logic such as protocol-independent fram-
ers, asynchronous transfer mode (ATM) framers,
packet-over-SONET (POS) interfaces, and framers for
HDLC for Internet protocol (IP), designers can build a
configurable interface retaining proven backplane
driver/receiver technology. Designers can also use the
device to drive high-speed data transfer across buses
within a system that are not SONET/SDH based. For
example, designers can build a 6.8 Gbits/s PCI-to-PCI
half bridge using our PCI soft core.
The ORT8850 family offers a clockless high-speed
interface for interdevice communication, on a board or
across a backplane. The built-in clock recovery of the
ORT8850 allows for higher system performance, eas-
ier-to-design clock domains in a multiboard system,
and fewer signals on the backplane. Network design-
ers will benefit from the backplane transceiver as a
network termination device. The backplane trans-
ceiver offers SONET scrambling/descrambling of data
and streamlined SONET framing, pointer moving, and
transport overhead handling, plus the programmable
logic to terminate the network into proprietary sys-
tems. For non-SONET application, all SONET func-
tionality is hidden from the user and no prior
networking knowledge is required. The 8850 also
offers 8B/10B coding in addition to SONET scram-
bling.
Also included on the device are three full-duplex, high-
speed parallel interfaces, consisting of 8-bit data, con-
trol (such as start-of-cell), and clock. The interface
delivers double data rate (DDR) data at rates up to
311 MHz (622 Mbits/s per pin), and converts this data
internal to the device into 32-bit wide data running at
half rate on one clock edge. Functions such as center-
ing the transmit clock in the transmit data eye are
done automatically by the interface. Applications
delivered by this interface include a parallel backplane
interface similar to the recently proposed RapidIO™
packet-based interface.
Table 1. ORCA® ORT8850 Family—Available FPGA Logic
Device
PFU Rows
PFU
Columns
ORT8850L
26
24
ORT8850H
46
44
Total
PFUs
624
2024
FPGA
User I/O
296
536
LUTs
4,992
16,192
EBR
Blocks
8
16
EBR Bits Usable
(K) Gates (K)
74 260—470
147 530—970
Note: The embedded core and interface are not included in the above gate counts.The usable gate counts range from a logic-only gate
count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC
(counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU).
Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used
as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded
block RAM (EBR) is counted as four gates per bit plus each block has an additional 25K gates. 7K gates are used for each PLL and
50K gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in
the gate calculations.
1 page  
Data Sheet
August 2001
ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Programmable FPGA Features
s High-performance platform design:
— 0.13 µm 7-level metal technology.
— Internal performance of >250 MHz.
— Over 600K usable system gates.
— Meets multiple I/O interface standards.
— 1.5 V operation (30% less power than 1.8 V oper-
ation) translates to greater performance.
s Traditional I/O selections:
— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/
Os.
— Per pin-selectable I/O clamping diodes provide
3.3 V PCI compliance.
— Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
— Two slew rates supported (fast and slew-limited).
— Fast-capture input latch and input flip-flop
(FF)/latch for reduced input setup time and zero
hold time.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
— Off-chip clock drive capability.
— Two-input function generator in output path.
s New programmable high-speed I/O:
— Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I & II), HSTL (Class I, III, IV), ZBT, and
DDR.
— Double-ended: LVDS, bused-LVDS, LVPECL.
— LVDS include optional on-chip termination resistor
per I/O and on-chip reference generation.
— Customer defined: ability to substitute arbitrary
standard-cell I/O to meet fast-moving standards.
s New capability to (de)multiplex I/O signals:
— New DDR on both input and output at rates up to
133 MHz (266 MHz effective rate).
— New 2x and 4x downlink and uplink capability per
I/O (i.e., 50 MHz internal to 200 MHz I/O).
s Enhanced twin-quad programmable function unit
(PFU):
— Eight 16-bit look-up tables (LUTs) per PFU.
— Nine user registers per PFU, one following each
LUT, and organized to allow two nibbles to act
independently, plus one extra for arithmetic opera-
tions.
— New register control in each PFU has two inde-
pendent programmable clocks, clock enables,
local set/reset, and data selects.
— New LUT structure allows flexible combinations of
LUT4, LUT5, new LUT6, 4 → 1 MUX, new
8 → 1 MUX, and ripple mode arithmetic functions
in the same PFU.
— 32 x 4 RAM per PFU, configurable as single- or
Agere Systems Inc.
dual-port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Soft-wired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU
through fast internal routing, which reduces rout-
ing congestion and improves speed.
— Flexible fast access to PFU inputs from routing.
— Fast-carry logic and routing to all four adjacent
PFUs for nibble-wide, byte-wide, or longer arith-
metic functions, with the option to register the PFU
carry-out.
s Abundant high-speed buffered and nonbuffered rout-
ing resources provide 2x average speed improve-
ments over previous architectures.
s Hierarchical routing optimized for both local and glo-
bal routing with dedicated routing resources. This
results in faster routing times with predictable and
efficient performance.
s SLIC provides eight 3-statable buffers, up to 10-bit
decoder, and PAL®-like and-or-invert (AOI) in each
programmable logic cell.
s Improved built-in clock management with dual-output
programmable phase-locked loops (PPLLs) provide
optimum clock modification and conditioning for
phase, frequency, and duty cycle from 20 MHz up to
416 MHz.
s New 200 MHz embedded quad-port RAM blocks,
two read ports, two write ports, and two sets of byte
lane enables. Each embedded RAM block can be
configured as:
— One—512 x 18 (quad-port, two read/two write)
with optional built-in arbitration.
— One—256 x 36 (dual-port, one read/one write).
— One—1K x 9 (dual-port, one read/one write).
— Two—512 x 9 (dual-port, one read/one write for
each).
— Two RAM with arbitrary number of words whose
sum is 512 or less by 18 (dual-port, one read/one
write).
— Supports joining of RAM blocks.
— Two 16 x 8-bit content addressable memory
(CAM) support.
— FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x 9.
— Constant multiply (8 x 16 or 16 x 8).
— Dual variable multiply (8 x 8).
s Embedded 32-bit internal system bus plus 4-bit par-
ity interconnects FPGA logic, microprocessor inter-
face (MPI), embedded RAM blocks, and embedded
backplane transceiver blocks with 100 MHz bus per-
formance. Included are built-in system registers that
act as the control and status center for the device.
5
5 Page 
Data Sheet
August 2001
ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
System-Level Features (continued)
Configuration
The FPGAs functionality is determined by internal con-
figuration RAM. The FPGAs internal initialization/con-
figuration circuitry loads the configuration data at
powerup or under system control. The configuration
data can reside externally in an EEPROM or any other
storage media. Serial EEPROMs provide a simple, low
pin-count method for configuring FPGAs.
The RAM is loaded by using one of several configura-
tion modes. Supporting the traditional master/slave
serial, master/slave parallel, and asynchronous periph-
eral modes, the Series 4 also utilizes its microproces-
sor interface and embedded system bus to perform
both programming and readback. Daisy chaining of
multiple devices and partial reconfiguration are also
permitted.
Other configuration options include the initialization of
the embedded-block RAM memories and FPSC mem-
ory as well as system bus options and bit stream error
checking. Programming and readback through the
JTAG (IEEE 1149.2) port is also available meeting in-
system programming (ISP) standards (IEEE 1532
Draft).
Additional Information
Contact your local Agere representative for additional
information regarding the ORCA Series 4 FPGA
devices, or visit our website at:
http://www.agere.com/orca
Agere Systems Inc.
11
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