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PDF OXFW911 Data sheet ( Hoja de datos )

Número de pieza OXFW911
Descripción IEEE1394 to ATA/ATAPI Native Bridge
Fabricantes ETC 
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FEATURES
S400 (50 Mbytes/s) compliant 1394-1995 Link and
Transaction layers
Compatible with 1394-1995 and 1394A Phys.
Microsoft Win98-Second Edition, Win2000 and Apple
MacOS generic driver support
SBP-2 Target Revision 4 compliant interface
Fully ATA-5 compliant (see T13-1321D)
Support for UDMA5 (ATA100)
Sustained data transfer of 35 MB/s
Supports PIO modes 0 to 4, DMA modes 0 to 2 and
Ultra DMA modes 0 to 5
ORB co-processor to accelerate translation of ORBs
to ATAPI commands
Supports ORB chaining for increased performance
DESCRIPTION
The OXFW911 is a high-performance 1394 to
ATA/ATAPI (IDE) native bridge with an integrated target
Serial Bus Protocol (SBP-2 ) controller. By supporting
the SBP-2 protocol, the device can use generic SBP-2
drivers available in the Microsoft Windows 98SE, Microsoft
Windows 2000, Microsoft Millennium and Apple MacOS
(8.4 to 9.04) operating systems. MacOS support also
includes booting from Firewire disk.
The device is ideally suited for smart-cable or tailgate
interface applications for removable-media drives, compact
flash card readers, CD-ROM, CD-R, CD-RW, DVD-ROM,
DVD-RAM and hard disk drives, allowing IDE drives to be
connected to a 1394 serial bus in a plug-and-play fashion.
Both ATA and ATAPI devices are supported using the
same firmware.
This highly integrated device offers a two-chip solution to
native bridge applications using an external 1394 PHY. The
device is compatible with both 1394-1995 and 1394A
PHYs.
The LINK controller complies with 1394-1995 and 1394A
specifications. The 1394 transaction layer and SBP-2
protocol is implemented using a combination of the
ARM7TDMI (low-power 32-bit RISC processor), an ORB
(Operational Request Block) hardware co-processor and a
high performance buffer manager.
The buffer manager has a RAM bandwidth of 800Mbps. It
provides storage for 1394 and ATA/ATAPI packets,
OXFW911
IEEE1394 to ATA/ATAPI Native Bridge
Data Sheet
High performance ATA command translation in
firmware using Reduced Block Command (RBC) set
Integrated 32-bit RISC processor (ARM7TDMI) with
on-chip scratch RAM
Optional External Serial ROM interface for
configuration data, user serial number, etc.
Integrated 512kb Flash memory
Blank Flash memory programming feature via 1394
bus
Firmware and Flash Programming Utilities supplied by
Oxford Semiconductor
3.3 Volts operation
Low Power CMOS
Ultra-thin 128-TQFP package (14 x 14 x 1 mm)
automatically storing them and passing them to the
appropriate destinations, without any intervention from the
processor. It also provides storage and manages the
sequencing of ORB fetching to reduce latency and improve
data throughput.
The configuration data including the IEEE OUI
(Organisational Unique Identifier) and device serial number
is stored in the Flash ROM which may be uploaded from
the 1394 bus, even when blank. The device also facilitates
firmware uploads from the 1394 bus.
The ORB co-processor translates ORBs as defined in the
SBP-2 protocol into ATA/ATAPI commands, and
automatically stores error/status messages at an address
specified by the host.
Concurrent operation of the ATA/ATAPI and 1394
interfaces are facilitated using the high throughput buffer
manager where LINK, ATAPI manager and ARM7TDMI
can perform interleaved accesses to the on-chip RAM
buffer. The high performance processor ensures that no
significant latency is incurred. The ATA command
translation is performed in firmware to meet RBC (Reduced
Block Commands) standard, T10-1228D. The ATA/ATAPI
Manager supports PIO modes 0 to 4, DMA modes 0 to 2
and Ultra DMA mode 0 to 5 and provides the interface to
the IDE bus. It is compliant with T13-1321D, ATA-5
specification, as well as support for ATA100.
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
© Oxford Semiconductor 2001
OXFW911 Data Sheet Revision 1.1 – Mar 2001
Part No. OXFW911-TQ-A

1 page




OXFW911 pdf
OXFORD SEMICONDUCTOR LTD.
OXFW911
3 PIN DESCRIPTIONS
1394 PHY-LINK interface
104, 105, 108, 109, 110, 111, 114,
115
116,117
119
121
102
103
ARM external interface
2, 3, 4, 5, 6, 9, 10, 11, 12, 13, 16,
17, 18, 19, 20, 24
35, 36, 37, 38, 41, 42, 43, 44, 45,
46, 49, 50, 51, 52, 53, 54, 60
123, 124, 27, 33
Dir1
I/O
I/O
I
O
IU
O
T_I/O
T_O
T_O
Name
PD[7:0]
CTL[1:0]
PHYCLK
LREQ
LINKON
LPS
D[15:0]
A[16:0]
CS#[3:0]
28 T_O OE#
34
61
IDE interface
86, 82, 80, 78, 74, 72, 70, 66, 65,
69, 71, 73, 77, 79, 81, 85
99, 97, 98
101, 100
T_O WE#
T_IU INT#
T_I/O ID[15:0]
T_O IA[2:0]
T_O ICS#[1:0]
63 T_O IDE_OE#
64
89
90
91
92
95
62
EEPROM interface
125
126
127
58
Miscellaneous Pins
56
128
22, 32, 31
57
T_O IRESET
T_I DMARQ
T_O DIOW#
T_O DIOR#
T_O IORDY
T_O DMACK#
T_I INTRQ
O GPO1
O GPO2
O GPO3
T_IU GPI
IU RESET#
T_O CKOUT
I TEST_SEL,
TEST[1:0]
IU UIF
Power and ground2
15, 8, 40, 48, 59, 76, 94, 107, 113
30, 21, 23, 68, 84, 88, 120
VDD AC VDD
VDD DC VDD
Data Sheet Rev 1.1
Description
Phy-Link Data Bus
Phy-Link Control Bus
49.152 MHz clock sourced by PHY
Link Request
Requests link to power up when in a low power mode
Indicates to phy that link is powered and ready
ARM external data bus
ARM external address bus
ARM external chip selects. CS0# is always used for program
ROM.
ARM external output enable. Active when reading data from
external devices including program ROM
Write Enable. Active when writing to external devices
External ARM interrupt
IDE data bus
IDE address bus
IDE chip select. Used to select the Command Block or
Control Block registers.
IDE output enable. Only used when external buffering is
required to drive IDE data bus
IDE interface reset
IDE interface write strobe
IDE interface read strobe
General Purpose Output 1
General Purpose Output 2
General Purpose Output 3
General Purpose Input
Global reset for the OXFW911. Active Low.
Clock output. 49.152 MHz clock output.
‘100’ = NORMAL OPERATION. Other settings are for
foundry test purposes only.
Leave unconnected to use internal Flash, tie low to use only
external device
Supplies power to output buffers in switching (AC) state
Power supply. Supplies power to core logic, input buffers
and output buffers in steady state
Page 5

5 Page





OXFW911 arduino
OXFORD SEMICONDUCTOR LTD.
OXFW911
Symbol
t2cyctyp
tcyc
t2cyc
tds
tdh
tdvs
tdvh
tfs
tli
tmli
tui
taz
tzah
tzad
tenv
trfs
trp
tiordyz
tziordy
tack
tss
Parameter
Typical sustained average two
cycle time
Cycle time allowing for clock
variations ( refer to ATA spec)
Two cycle time allowing for clock
variations ( refer to ATA spec )
Data setup time at recipient
Data hold time at recipient
Data valid setup time at sender
(from data bus being valid until
STROBE edge )
Data valid hold time at sender
(from STROBE edge until data
may become invalid
First STROBE time (for device to
first negate DSTROBE from
STOP during a data-in burst)
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output
drivers to release (from being
asserted or negated)
Minimum delay time required for
output drivers to assert or negate
(from released state)
Envelope time ( from DMACK# to
STOP and HDMARDY# during
data-out burst initiation
Ready-to-final-STROBE time ( no
STROBE edges shall be sent this
long after the negation of
DDMARDY#
Ready-to-pause time ( time that
recipient shall wait to initiate
pause after negating DMARDY# )
Pull-up time before allowing
IORDY to be released
Minimum time a device shall wait
before driving IORDY
Setup and hold times for
DMACK# (before assertion or
negation )
Time from STROBE edge to
negation of DMARQ or assertion
of STOP (when sender terminates
a burst )
Mode 3
min
100
39
86
7
5
20
6
0
0
20
0
20
0
20
100
0
20
50
Mode 3 Mode 4 Mode4
max min max
60
25
57
5
5
6
6
130 0 120
100 0 100
20
0
10 10
20
0
55 20 55
60 60
100
20 20
0
20
50
Mode5
min
40
20
40
4.0
4.6
4.8
4.8
0
0
20
0
20
50
Mode5
max
90
75
20
0
10
20
0
50
50
85
20
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 7a: OXFW911 Ultra DMA timings (cont)
Data Sheet Rev 1.1
Page 11

11 Page







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