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PDF OZ6812T Data sheet ( Hoja de datos )
| Número de pieza | OZ6812T | |
| Descripción | ACPI CardBus Controller | |
| Fabricantes | ETC | |
| Logotipo |  |
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OZ6812
ACPI CardBus Controller
FEATURES
The OZ6812 is a PCMCIA R2/CardBus controller, providing
the most advanced design flexibility for PC Cards that
interface with advanced notebook designs.
• ACPI-PCI Bus Power Management Interface
Specification Rev 1.1 Compliant
• Supports OnNow LAN wakeup, OnNow Ring Indicate,
PCI CLKRUN#, PME#, and CardBus CCLKRUN#
• Compliant with PCI specification V2.2, 1998 PC Card
Standard 7.0
• Yenta™ PCI to PCMCIA CardBus Bridge register
compatible
• ExCA (Exchangeable Card Architecture) compatible
registers mappable in memory and I/O space
• IntelTM 82365SL PCIC Register Compatible
• Supports PCMCIA_ATA Specification
• Supports 5V/3.3V PC Cards and 3.3V CardBus cards
• Supports single PC Card or CardBus slot with hot
insertion and removal
• Supports multiple FIFOs for PCI/CardBus data transfer
• Supports Direct Memory Access for PC/PCI and
PCI/Way on PC Card socket
• Programmable interrupt protocol: PCI, PCI+ISA,
PCI/Way, or PC/PCI interrupt signaling modes
• Win’98 IRQ and PC-98/99 compliant
• Parallel or Serial interface for socket power control
devices including Micrel and TI
• Zoomed Video Support
• Integrated PC 98/99 -Subsystem Vendor ID support,
with auto lock bit
• LED Activity Pins
ORDERING INFORMATION
OZ6812T - 144pin LQFP
OZ6812B - 144pin Mini-BGA
GENERAL DESCRIPTION
The OZ6812 is an ACPI and PC98/99 logo certified, high
performance, single slot PC Card controller with a
synchronous 32-bit bus master/target PCI interface. This
PC Card to PCI bridge host controller is compliant with the
1998 PC Card Standard. This standard incorporates the
new 32-bit CardBus while retaining the 16-bit PC Card
specification as defined by PCMCIA release 2.1. CardBus
is intended to support “temporal” add-in functions on PC
Cards, such as Memory cards, Network interfaces,
FAX/Modems and other wireless communication cards, etc.
The high performance and capability of the CardBus
interface will enable the development of many new
functions and applications.
The OZ6812 CardBus controller is compliant with the latest
ACPI-PCI Bus Power Management Interface Specification.
It supports all four power states and the PME# function for
maximum power savings and ACPI compliance. The device
also provides a power-down mode to allow host software to
reduce power consumption further by stopping internal
clock distribution as well as the PC Card socket clock. In
addition, an advanced CMOS process is utilized to
minimize system power consumption.
The OZ6812 single PCMCIA socket supports 3.3V/5V 8/16-
bit PC Card R2 card or 32-bit CardBus R3 card. The R2
card support is compatible with the Intel 82365SL PCIC
controller, and the R3 card support is fully compliant with
the 1998 PC Card Standard CardBus specification. The
OZ6812 is a stand alone device, which means that it does
not require an additional buffer chip for the PC Card socket
interface. In addition, the OZ6812 supports dynamic PC
Card hot insertion and removal, with auto configuration
capabilities.
The OZ6812 is fully compliant with the 33Mhz PCI Bus
specification, V2.2. It supports a master device with
internal CardBus direct data transfer. The OZ6812
implements a FIFO data buffer architecture between the
PCI bus and CardBus socket interface to enhance data
transfers to CardBus devices. The bi-directional FIFO
buffer (composed of 16 double words) permits the OZ6812
to accept data from a target bus (PCI or CardBus interface)
while simultaneously transferring data. This architecture
not only speeds up data transfers but also prevents system
deadlocks.
04/25/00
Copyright 2000 by O2Micro
OZ6812-SF-1.5
All Rights Reserved
Page 1
Patent Pending
1 page  
OZ6812
Pin Name
PAR
PCI_CLK
RST#
GNT#
REQ#
Description
Parity: This pin generates PCI parity and ensures
even parity across AD[31:0] and C/BE[3:0]#.
During the address phase, PAR is valid after one
clock. With data phases, PAR is stable one clock
after a write or read transaction.
PCI Clock: This input provides timing for all
transactions on the PCI bus to and from the
OZ6812. All PCI bus signals, except RST#, are
sampled and driven on the rising edge of
PCI_CLK. This input can be operated at
frequencies from 0 to 33 MHz.
Device Reset: This input is used to initialize all
registers and internal logic to their reset states
and place most OZ6812 pins in a HIGH-
impedance state.
Grant: This signal indicates that access to the bus
has been granted.
Request: This signal indicates to the arbiter that
the OZ6812 requests use of the bus.
Pin Number
LQFP
BGA
36 L3
21 G4
20 G2
2 B2
1 A1
Input Type
TTL I/O
Power
Rail
PCI_Vcc
Drive
PCI
Spec
-
I PCI_Vcc
-
-
I AUX_Vcc
-
TTL I
- TO
PCI_Vcc
PCI_Vcc
PCI
Spec
PCI
Spec
Power Control and General Interface Pins
Pin Name
RI_OUT/
PME#
Description
Ring Indicate Out: This pin is Ring Indicate
when the following occurs while O2 Mode Control
B Register (index 2Eh) bit 7 is set to 1:
1) Power Control (Index+02h) bit 7 set to 1
2) Interrupt and General Control (Index+03h)
bit 7 set to 1
3) PCI O2Micro Control 2 (Offset: D4h) bit X =
0
Pin Number
LQFP
BGA
59 M8
Input Type
- TO
Power
Rail
Aux_Vcc
Drive
4mA
Power Management Event: A power
management event is the process by which the
OZ6812 can request a change of its power
consumption state. Usually, a PME occurs
during a request to change from a power saving
state to the fully operational state.
SPKR_OUT# Speaker Output: This output can be used to
62
K8 TTL I/O Aux_Vcc 12mA
support PC Card audio output. See O2 Mode E
Register (Index + 3Eh), bit 1.
MF[6:0]
Multifunction Terminal [6:0]: See PCI 69-67, 65-64, L10, K9, N11, TTL I/O Aux_Vcc 12mA
Multifunction MUX Register (Offset:08h).
61-60
L9, N10-9, L8
SUSPEND# Suspend: This signal is used to protect the
internal registers from clearing when the PCI
70
N12
TTL I Aux_Vcc
-
RST# signal is asserted. When low, this signal is
used to mask the PCI RESET during suspend.
This pin can be used during suspend to prevent
controller reset.
OZ6812-SF-1.5
Page 5
5 Page 
Power, Ground, and Reserved Pins
OZ6812
Pin Name
Aux_VCC
CORE_VCC
PCI_VCC
GND
Description
Auxiliary VCC: This pin is connected to the
system’s 3.3/5V power supply. For the device
to 5V tolerant, connect to +5V power.
CORE_VCC: This pin provides power to the
core circuitry of the OZ6812. It must be
connected to a 3.3V power supply.
PCI Bus VCC: These pins can be connected to
either a 3.3V or5V power supply. The PCI bus
interface will operate at the voltage applied to
these pins, independent of the voltage applied
to other OZ6812 pin groups.
System Ground
Pin Number
LQFP
BGA
63 M9
14, 66, 86,
102, 122,
138
18, 30, 44,
50
F4, M10,
H10, D12,
D8, B4
G3, K2,
M4, K6
6, 22, 42,
58, 78, 94,
114, 130
D3, H1,
L4, N8,
K11, F13,
C10, A6
Input
-
-
-
-
Type
PWR
PWR
PWR
GND
Power
Rail
-
-
-
-
Drive
-
-
-
-
Legend
I/O Type
I
I-PU
I-PU Schmitt
O
OD
TO
TO-PU
OD-PU
PWR
Description
Input Pin
Input pin with internal pull-up
Input pin with internal pull-up and Schmitt
trigger
Output
Open-drain
Tri-state output
Tri-state output with internal pull-up
Open-drain output with internal pull-up
Power pin
Power Rail
1
2
3
Source of Output’s Power
AUX_VCC: outputs powered from AUX_VCC
SOCKET_VCC: outputs powered from the socket
PCI_VCC: outputs powered from PCI bus power
supply
4 CORE_VCC: outputs powered from the CORE_VCC
OZ6812-SF-1.5
Page 11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet OZ6812T.PDF ] | |
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