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PDF S80C186EA20 Data sheet ( Hoja de datos )
| Número de pieza | S80C186EA20 | |
| Descripción | 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS | |
| Fabricantes | Intel Corporation | |
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80C186EA 80C188EA AND 80L186EA 80L188EA
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Y 80C186 Upgrade for Power Critical Applications
Y Fully Static Operation
Y True CMOS Inputs and Outputs
Y Integrated Feature Set
Static 186 CPU Core
Power Save Idle and Powerdown
Modes
Clock Generator
2 Independent DMA Channels
3 Programmable 16-Bit Timers
Dynamic RAM Refresh Control Unit
Programmable Memory and
Peripheral Chip Select Logic
Programmable Wait State Generator
Local Bus Controller
System-Level Testing Support
(High Impedance Test Mode)
Y Speed Versions Available (5V)
25 MHz (80C186EA25 80C188EA25)
20 MHz (80C186EA20 80C188EA20)
13 MHz (80C186EA13 80C188EA13)
Y Speed Versions Available (3V)
13 MHz (80L186EA13 80L188EA13)
8 MHz (80L186EA8 80L188EA8)
Y Direct Addressing Capability to
1 Mbyte Memory and 64 Kbyte I O
Y Supports 80C187 Numeric Coprocessor
Interface (80C186EA only)
Y Available in the Following Packages
68-Pin Plastic Leaded Chip Carrier
(PLCC)
80-Pin EIAJ Quad Flat Pack (QFP)
80-Pin Shrink Quad Flat Pack (SQFP)
Y Available in Extended Temperature
Range (b40 C to a85 C)
The 80C186EA is a CHMOS high integration embedded microprocessor The 80C186EA includes all of the
features of an ‘‘Enhanced Mode’’ 80C186 while adding the additional capabilities of Idle and Powerdown
Modes In Numerics Mode the 80C186EA interfaces directly with an 80C187 Numerics Coprocessor
272432 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
October 1995
Order Number 272432-003
COPYRIGHT INTEL CORPORATION 1995
1
1 page  
80C186EA 80C188EA 80L186EA 80L188EA
272432 – 4
272432 – 3
(A) Crystal Connection
(B) Clock Connection
NOTE
The L1C1 network is only required when using a third-overtone crystal
Figure 2 Clock Configurations
80C186EA PERIPHERAL
ARCHITECTURE
The 80C186EA has integrated several common sys-
tem peripherals with a CPU core to create a com-
pact yet powerful system The integrated peripher-
als are designed to be flexible and provide logical
interconnections between supporting units (e g the
interrupt control unit supports interrupt requests
from the timer counters or DMA channels)
The list of integrated peripherals include
4-Input Interrupt Control Unit
3-Channel Timer Counter Unit
2-Channel DMA Unit
13-Output Chip-Select Unit
Refresh Control Unit
Power Management logic
The registers associated with each integrated peri-
heral are contained within a 128 x 16 register file
called the Peripheral Control Block (PCB) The PCB
can be located in either memory or I O space on
any 256 byte address boundary
Figure 3 provides a list of the registers associated
with the PCB when the processor’s Interrupt Control
Unit is in Master Mode In Slave Mode the defini-
tions of some registers change Figure 4 provides
register definitions specific to Slave Mode
Interrupt Control Unit
The 80C186EA can receive interrupts from a num-
ber of sources both internal and external The Inter-
rupt Control Unit (ICU) serves to merge these re-
quests on a priority basis for individual service by
the CPU Each interrupt source can be independent-
ly masked by the Interrupt Control Unit or all inter-
rupts can be globally masked by the CPU
Internal interrupt sources include the Timers and
DMA channels External interrupt sources come
from the four input pins INT3 0 The NMI interrupt
pin is not controlled by the ICU and is passed direct-
ly to the CPU Although the timers only have one
request input to the ICU separate vector types are
generated to service individual interrupts within the
Timer Unit
Timer Counter Unit
The 80C186EA Timer Counter Unit (TCU) provides
three 16-bit programmable timers Two of these are
highly flexible and are connected to external pins for
control or clocking A third timer is not connected to
any external pins and can only be clocked internally
However it can be used to clock the other two timer
channels The TCU can be used to count external
events time external events generate non-repeti-
tive waveforms generate timed interrupts etc
5
5
5 Page 
80C186EA 80C188EA 80L186EA 80L188EA
Pin
Name
VCC
VSS
CLKIN
OSCOUT
CLKOUT
RESIN
RESOUT
PDTMR
NMI
Table 3 Pin Descriptions
Pin Input Output
Type Type States
Description
P
G
I A(E)
POWER connections consist of six pins which must be shorted
externally to a VCC board plane
GROUND connections consist of five pins which must be shorted
externally to a VSS board plane
CLocK INput is an input for an external clock An external
oscillator operating at two times the required processor operating
frequency can be connected to CLKIN For crystal operation
CLKIN (along with OSCOUT) are the crystal connections to an
internal Pierce oscillator
O H(Q) OSCillator OUTput is only used when using a crystal to generate
R(Q) the external clock OSCOUT (along with CLKIN) are the crystal
P(Q) connections to an internal Pierce oscillator This pin is not to be
used as 2X clock output for non-crystal applications (i e this pin is
N C for non-crystal applications) OSCOUT does not float in
ONCE mode
O H(Q) CLocK OUTput provides a timing reference for inputs and outputs
R(Q) of the processor and is one-half the input clock (CLKIN)
P(Q) frequency CLKOUT has a 50% duty cycle and transistions every
falling edge of CLKIN
I A(L)
RESet IN causes the processor to immediately terminate any bus
cycle in progress and assume an initialized state All pins will be
driven to a known state and RESOUT will also be driven active
The rising edge (low-to-high) transition synchronizes CLKOUT with
CLKIN before the processor begins fetching opcodes at memory
location 0FFFF0H
O H(0) RESet OUTput that indicates the processor is currently in the
R(1) reset state RESOUT will remain active as long as RESIN remains
P(0) active When tied to the TEST BUSY pin RESOUT forces the
80C186EA into Numerics Mode
I O A(L) H(WH) Power-Down TiMeR pin (normally connected to an external
R(Z) capacitor) that determines the amount of time the processor waits
P(1) after an exit from power down before resuming normal operation
The duration of time required will depend on the startup
characteristics of the crystal oscillator
I A(E)
Non-Maskable Interrupt input causes a Type 2 interrupt to be
serviced by the CPU NMI is latched internally
TEST BUSY
(TEST)
I
A(E)
AD15 0
(AD7 0)
I O S(L)
H(Z)
R(Z)
P(X)
TEST BUSY is sampled upon reset to determine whether the
80C186EA is to enter Numerics Mode In regular operation the pin
is TEST TEST is used during the execution of the WAIT
instruction to suspend CPU operation until the pin is sampled
active (low) In Numerics Mode the pin is BUSY BUSY notifies the
80C186EA of 80C187 Numerics Coprocessor activity
These pins provide a multiplexed Address and Data bus During
the address phase of the bus cycle address bits 0 through 15 (0
through 7 on the 8-bit bus versions) are presented on the bus and
can be latched using ALE 8- or 16-bit data information is
transferred during the data phase of the bus cycle
NOTE
Pin names in parentheses apply to the 80C188EA and 80L188EA
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