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S9418 PDF даташит

Спецификация S9418 изготовлена ​​​​«ETC» и имеет функцию, называемую «Quad 8-Bit Nonvolatile DACPOT Electronic Potentiometer With a Mute Control Input».

Детали детали

Номер произв S9418
Описание Quad 8-Bit Nonvolatile DACPOT Electronic Potentiometer With a Mute Control Input
Производители ETC
логотип ETC логотип 

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S9418 Даташит, Описание, Даташиты
SUMMIT
MICROELECTRONICS, Inc.
Quad 8-Bit Nonvolatile DACPOT™ Electronic Potentiometer
With a Mute Control Input
S9418
FEATURES
• Four 8-Bit DACS
— Differential Non-linearity - ±0.5LSB max
— Integral Non-Linearity Error - ±1LSB max
• Each DAC has Independent Reference Inputs
— Output Buffer Amplifiers Swing Rail-to-Rail
— Ground to VDD Reference Input Range
• Each DAC’s Digital Inputs Maintained in
EEPROM
• Power-On Reset Reloads Registers with
Nonvolatile Data
• Simple Serial Interface for Reading and Writing
DAC values, SPI™ and QSPI™ compatible.
• Fully operational from 2.7V to 5.5V
• Low Power, 4mW max at +5V
OVERVIEW
The S9418 DACPOT™ is a serial input, voltage output,
quad 8-bit digital to analog converter. The S9418 oper-
ates from a single +2.7V to +5.5V supply. Internal preci-
sion buffers swing rail-to-rail and the reference input
range includes both ground and the positive supply.
The S9418 integrates four 8-bit DACs and their associ-
ated circuits which include; an enhanced unity gain opera-
tional amplifier output, an 8-bit data latch, an 8-bit non-
volatile register and an industry standard serial interface
for reading and writing data to the DACs’ data latches and
registers. The DACs are independently programmable
and each has its own electrically isolated Vreference
inputs.
FUNCTIONAL BLOCK DIAGRAM
RDY/BSY
Programming
Memory
Controller
Memory Control
8-bit E2PROM
Serial Data In 8-bit Data Register
CS
DI
CLK
MUTE
VDD
GND
Control
Logic
Serial Data Out
8-bit DAC
AMP
DAC Section 0
VREFH0
VOUT0
VREFL0
DAC Section 1
DAC Section 2
DAC Section 3
VREFH1
VOUT1
VREFL1
VREFH2
VOUT2
VREFL2
VREFH3
VOUT3
VREFL3
DO
2023 ILL2 1.2
SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 1999
2023 1.5 4/24/99
Characteristics subject to change without notice
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S9418 Даташит, Описание, Даташиты
S9418
PINOUT and SIGNAL DEFINITION
VREFH1 1
VREFH0 2
VDD 3
RDY/BSY 4
CLK 5
CS 6
DI 7
DO 8
MUTE 9
GND 10
20 VREFH2
19 VREFH3
18 VOUT0
17 VOUT1
16 VOUT2
15 VOUT3
14 VREFL3
13 VREFL2
12 VREFL1
11 VREFL0
2023 ILL1 1.2
Pin Name Function
1, 2 VREFH
20, 19
Vreference High:
VREFH VDD > VREFL
3 VDD
Power Supply Voltage
4 RDY/BSY Ready/Busy: open drain output
indicating status of nonvolatile
write operations
5 CLK
Clock Input Pin: used for serial
data communication
6 CS
Chip Select: When high deselects
the device and places it in a low
power mode
7 DI
Data Input: serial data input pin
8 DO
Data Output: serial data output pin
9 MUTE
When active forces VOUT to VREFL
10 GND
Power Supply Ground
11, 12 VREFL
13, 14
Vreference Low
15, 16 VOUT
17, 18
DAC Output: buffered D to A
converter output
The analog outputs of the S9418 can be programmed to
any one of 256 individual voltage steps. Each step value
is 1/256th of the voltage differential between VrefH and
VrefL of the respective DAC. Once programmed these
settings can be retained in nonvolatile memory during all
power conditions and will be automatically recalled upon
a power-up sequence. Each DAC can be independently
read without affecting the output voltage during the read
cycle. In addition each output can be adjusted an unlim-
ited number of times without altering the value stored in
the nonvolatile memory.
DEVICE OPERATION
Analog Section
The S9418 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts 8-bit digital inputs into equivalent analog
output voltages in proportion to the applied reference
voltage.
Reference inputs
The voltage differential between the VREFL and VREFH
inputs sets the full-scale output voltage for its respective
DAC. VREFL must be equal to or greater than ground
(positive voltage). VREFH must be greater (more positive)
than VREFL or equal to VDD.
Output Buffer Amplifiers
The voltage outputs are from precision unity-gain follow-
ers that can slew up to 1V/µs. The outputs can swing from
VREFL to VREFH. With a 0V to 5V output transition the
amplifier outputs typically settle to 1LSB in 50µs.
DIGITAL INTERFACE
The S9418 employs a common 4-wire serial interface. It
is comprised of a Clock (CLK), Chip Select (CS) and Data
In (DI) input and a Data Out (DO) output. Data is clocked
into the device on the clock’s rising edge and out of the
device on the clock’s falling edge. Data is shifted in and
out MSB first. DO only becomes active after the device
has been selected and after a valid read command and
address has been received.
All data transfers are initiated after CS goes LOW and a
logic ‘1’ is clocked into the device. This first data transfer
is the start bit and must precede all operations. Following
the start bit are two command bits used to specify which
of four commands to execute. The next two bits are the
address bits used to select one of the four DACs. The
action of the next eight clock cycles will be dependent
upon the command issued.
2023 1.5 4/24/99
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S9418 Даташит, Описание, Даташиты
S9418
S CH CL AH AL
1 0 0 A A NV Enable - Data Don’t Care
1 0 1 A A Write Command - Data In
1 1 0 A A Read - Data Out
1 1 1 A A Recall -Data Don’t Care
TABLE 1. COMMAND FORMAT
2023 PGM T1 1.0
Internally there are four DACs and associated with each
are two registers. There is one data register that is used
by the DAC to hold the digital value it converts. There is
also one nonvolatile register that holds the default value
that can be recalled into the data register during power-
up or by executing the Recall command.
READ
Read operations are initiated by taking CS LOW and
clocking in a start bit followed by the read command and
the address of the data register to be read. The next eight
clocks will output on the DO pin the contents of the
selected data register. This read will not affect the con-
tents of the register or the output of the DAC. Refer to
Figure 1 for an illustration of the sequence of bus condi-
tions for a read operation.
WRITE
Write operations are initiated by taking CS LOW and
clocking in a start bit followed by the write command and
the address of the data register to be written. This action
is followed by the host clocking eight bits of data into the
register, MSB first. The output of the selected DAC will
change as the last bit is clocked into the device. At this
point the clock counter will reset the command register,
requiring a full sequence to be initiated in order to write to
the DAC again. NOTE: This write operation does not
affect the contents of the nonvolatile register. Therefore,
the nonvolatile register can contain the power-on default
settings (e.g. volume), and the write DAC command can
be used to make situational adjustments. Refer to Figure
2 for an illustration of the sequence of bus conditions for
a write operation.
CS
CLK
DI
DO
RDY/BSY
S
T
C1 C0 A1 A0
A
R
T
Hi Z D7 D6 D5 D4 D3 D2 D1 D0
Pulled Up to VDD
Hi Z
2023 ILL3 1.0
FIGURE 1. READ SEQUENCE
2023 1.5 4/24/99
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Номер в каталогеОписаниеПроизводители
S9418Quad 8-Bit Nonvolatile DACPOT Electronic Potentiometer With a Mute Control InputETC
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