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Número de pieza SA1110
Descripción Intel StrongARM SA-1110 Microprocessor
Fabricantes Intel Corporation　
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Intel® StrongARM* SA-1110
Microprocessor
Developer’s Manual
June 2000
Notice: This document contains information on products in the design phase of development. Do
not finalize a design with this information. Revised information will be published when the product is
available. Verify with your local Intel sales office that you have the latest technical information before
finalizing a design.
Order Number: 278240-003

1 page




SA1110 pdf
9 System Control Module ...............................................................................................9–1
9.1 General-Purpose I/O .........................................................................................9–1
9.1.1 GPIO Register Definitions..............................................................................9–2
9.1.1.1 GPIO Pin-Level Register (GPLR) ............................................................9–3
9.1.1.2 GPIO Pin Direction Register (GPDR) ......................................................9–4
9.1.1.3 GPIO Pin Output Set Register (GPSR) and Pin Output
Clear Register (GPCR) ............................................................................9–5
9.1.1.4 GPIO Rising-Edge Detect Register (GRER) and
Falling-Edge Detect Register (GFER) .....................................................9–6
9.1.1.5 GPIO Edge Detect Status Register (GEDR) ...........................................9–7
9.1.1.6 GPIO Alternate Function Register (GAFR)..............................................9–8
9.1.2 GPIO Alternate Functions..............................................................................9–9
9.1.2.1 3.6864 MHz Option for GP 27 Alternate Output Function ..................... 9–10
9.1.3 GPIO Register Locations ............................................................................. 9–10
9.2 Interrupt Controller .......................................................................................... 9–11
9.2.1 Interrupt Controller Register Definitions....................................................... 9–12
9.2.1.1 Interrupt Controller Pending Register (ICPR) ........................................9–12
9.2.1.2 Interrupt Controller IRQ Pending Register (ICIP) and
FIQ Pending Register (ICFP) ................................................................ 9–14
9.2.1.3 Interrupt Controller Mask Register (ICMR) ............................................ 9–15
9.2.1.4 Interrupt Controller Level Register (ICLR) ............................................. 9–16
9.2.1.5 Interrupt Controller Control Register (ICCR) ......................................... 9–17
9.2.2 Interrupt Controller Register Locations ........................................................ 9–18
9.3 Real-Time Clock.............................................................................................. 9–18
9.3.1 RTC Counter Register (RCNR) ................................................................... 9–18
9.3.2 RTC Alarm Register (RTAR) ....................................................................... 9–19
9.3.3 RTC Status Register (RTSR)....................................................................... 9–19
9.3.4 RTC Trim Register (RTTR).......................................................................... 9–20
9.3.5 Trim Procedure ............................................................................................ 9–20
9.3.5.1 Oscillator Frequency Calibration ...........................................................9–20
9.3.5.2 RTTR Value Calculations ...................................................................... 9–21
9.3.6 Real-Time Clock Register Locations ...........................................................9–22
9.4 Operating System Timer ................................................................................. 9–22
9.4.1 OS Timer Count Register (OSCR)............................................................... 9–23
9.4.2 OS Timer Match Registers 0–3 (OSMR 0, OSMR 1, OSMR 2, OSMR 3)... 9–23
9.4.3 OS Timer Watchdog Match Enable Register (OWER) ................................ 9–23
9.4.4 OS Timer Status Register (OSSR) .............................................................. 9–24
9.4.5 OS Timer Interrupt Enable Register (OIER) ................................................ 9–25
9.4.6 Watchdog Timer .......................................................................................... 9–25
9.4.7 OS Timer Register Locations....................................................................... 9–26
9.5 Power Manager .............................................................................................. 9–26
9.5.1 Run Mode .................................................................................................... 9–26
9.5.2 Idle Mode ..................................................................................................... 9–26
9.5.2.1 Entering Idle Mode ................................................................................ 9–27
9.5.2.2 Exiting Idle Mode ................................................................................... 9–27
9.5.3 Sleep Mode..................................................................................................9–28
9.5.3.1 CPU Preparation for Sleep Mode .......................................................... 9–28
9.5.3.2 Events Causing Entry into Sleep Mode ................................................. 9–28
9.5.3.3 The Sleep Shutdown Sequence ............................................................ 9–28
9.5.3.4 During Sleep Mode................................................................................ 9–29
9.5.3.5 The Sleep Wake-Up Sequence ............................................................. 9–29
SA-1110 Developer’s Manual
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SA1110 arduino
11.10.10.2Transmit Underrun Status (TUR) (read/write, maskable interrupt) ...11–102
11.10.10.3Receiver Abort Status (RAB) (read/write, nonmaskable interrupt) ...11–102
11.10.10.4Transmit FIFO Service Request Flag (TFS) (read-only,
maskable interrupt) ............................................................................11–103
11.10.10.5Receive FIFO Service Request Flag (RFS) (read-only,
maskable interrupt) ............................................................................11–103
11.10.10.6Framing Error Status (FRE) (read/write, nonmaskable interrupt) .....11–104
11.10.11HSSP Status Register 1 .........................................................................11–105
11.10.11.1Receiver Synchronized Flag (RSY) (read-only, noninterruptible) .....11–105
11.10.11.2Transmitter Busy Flag (TBY) (read-only, noninterruptible) ...............11–105
11.10.11.3Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)..11–105
11.10.11.4Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)......11–105
11.10.11.5End-of-Frame Flag (EOF) (read-only, noninterruptible)....................11–105
11.10.11.6CRC Error Status (CRE) (read-only, noninterruptible)......................11–106
11.10.11.7Receiver Overrun Status (ROR) (read-only, noninterruptible) ..........11–106
11.10.12UART Register Locations .......................................................................11–108
11.10.13HSSP Register Locations .......................................................................11–108
11.11 Serial Port 3 – UART...................................................................................11–109
11.11.1 UART Operation ......................................................................................11–109
11.11.1.1 Frame Format....................................................................................11–110
11.11.1.2 Baud Rate Generation.......................................................................11–110
11.11.1.3 Receive Operation.............................................................................11–110
11.11.1.4 Transmit Operation............................................................................11–111
11.11.1.5 Transmit and Receive FIFOs.............................................................11–111
11.11.1.6 CPU and DMA Register Access Sizes ..............................................11–111
11.11.2 UART Register Definitions.......................................................................11–111
11.11.3 UART Control Register 0 .........................................................................11–112
11.11.3.1 Parity Enable (PE) .............................................................................11–112
11.11.3.2 Odd/Even Parity Select (OES) ..........................................................11–112
11.11.3.3 Stop Bit Select (SBS) ........................................................................11–112
11.11.3.4 Data Size Select (DSS) .....................................................................11–112
11.11.3.5 Sample Clock Enable (SCE) .............................................................11–113
11.11.3.6 Receive Clock Edge Select (RCE) ....................................................11–113
11.11.3.7 Transmit Clock Edge Select (TCE)....................................................11–113
11.11.4 UART Control Registers 1 and 2 .............................................................11–115
11.11.4.1 Baud Rate Divisor (BRD)...................................................................11–115
11.11.5 UART Control Register 3 .........................................................................11–116
11.11.5.1 Receiver Enable (RXE) .....................................................................11–116
11.11.5.2 Transmitter Enable (TXE) ..................................................................11–116
11.11.5.3 Break (BRK) ......................................................................................11–116
11.11.5.4 Receive FIFO Interrupt Enable (RIE) ................................................11–117
11.11.5.5 Transmit FIFO Interrupt Enable (TIE) ................................................11–117
11.11.5.6 Loopback Mode (LBM) ......................................................................11–117
11.11.6 UART Data Register ................................................................................11–118
11.11.7 UART Status Register 0 ..........................................................................11–120
11.11.7.1 Transmit FIFO Service Request Flag (TFS) (read-only,
maskable interrupt) ............................................................................11–120
11.11.7.2 Receive FIFO Service Request Flag (RFS) (read-only,
maskable interrupt)11–120
11.11.7.3 Receiver Idle Status (RID) (read/write, maskable interrupt) ..............11–121
11.11.7.4 Receiver Begin of Break Status (RBB) (read/write,
nonmaskable interrupt) ......................................................................11–121
11.11.7.5 Receiver End of Break Status (REB) (read/write,
SA-1110 Developer’s Manual
xi

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