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PDF SA3488 Data sheet ( Hoja de datos )
| Número de pieza | SA3488 | |
| Descripción | CMOS 256 X 256 DIGITAL SWITCHING MATRIX | |
| Fabricantes | Sames | |
| Logotipo |  |
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SA3488
SA3488
CMOS 256 X 256 DIGITAL SWITCHING MATRIX
FEATURES
s Hardware (pin-to-pin) and software s Actual input-output channel
compatible with M088 and M3488
connections stored and modified via
s 256 input and 256 output channel digital
switching matrix
an on chip 8-bit parallel microprocessor
interface
s Building block designed for large s 6 main “Functions” or “Instructions”
capacity electronic exchanges, sub-
available
systems and PABX
s Typical Bit Rate : 2Mbit/s
s Non-blocking single stage and higher s Typical Synchronization Rate : 8KHz
capacity blocks (512 or 1024 channels)
(time frame is 125µs)
s European and U.S. standard s 5V power supply with internally
compatible (32/24 serial channels per
generated bias voltage
frame)
s MOS & TTL input/output levels
s PCM inputs and outputs mutually
compatible
compatible
DESCRIPTION
The SA3488 is a non-blocking digital
switching matrix that is capable of routing
256 input channels to any of 256 output
channels. Data is fed into and out of the
device via eight serial PCM input and
output channels at 2MBits/sec. The device
can connect or disconnect each input
channel with any output channel, as well as
carry out other functions which are user
programmable via an eight bit parallel
microprocessor interface. The SA3488
sees its primary use as a building block in
high volume electronic exchanges, voice
data PABX and other standard data
communications applications. It can be
easily configured for operation in PCM 24
or PCM 30 formats.
PIN CONNECTIONS:
SA3488
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1
1 page  
SA3488
A.C. ELECTRICAL CHARACTERISTICS (T = 0 to 70°C, V = 5V ±5%)
amb CC
All A.C. characteristics are valid 250µs after VCC and clock have been applied. CL is the max.
capacitive load and RL the test pull up resistor.
Signal
CK
(clock)
SYNC
PCM input
Busses
PCM
Output
Busses
Symbol
tCK
tWL
t
WH
tR
tF
tSL
t
HL
tSH
tWH
tS
tH
tPDmin
tPDmax
Parameter
Test Condition
Clock Period
Clock Low Level Width
Clock High Level Width
Rise Time
Fall Time
Low Level Setup Time
Low Level Hold Time
High Level Setup Time
High Level Width
Setup Time
Hold Time
Propagation time
CL = 50pf,RL=2K
referred to CK low level
Propagation time
CL = 50pf,RL=2K
referred to CK high level
Min.
230
100
100
80
40
80
tCK
-5
45
45
Typ. Max. Unit
ns
ns
ns
25 ns
25 ns
ns
ns
ns
ns
ns
ns
ns
200 ns
RESET
WR
RD
tSL Low Level Setup Time
tHL Low Level Hold Time
tSH High Level Setup Time
tWH High Level Width
100
50
90
tCK
tWL Low Level Width
150
tWH High Level Width
tCK
tREP Repetition Interval
tREP = 40+2 tCK +
see
between Active Pulses + tWL(CK) +
formula
tSH High Level Setup Time + tR(CK)
0
to Active Read Strobe
tHH High Level Hold Time
from Active Read Strobe
20
tR Rise Time
tF Fall Time
tWL Low Level Width
180
tWH High Level Width
tCK
tREP Repetition Interval
tREP = 40+2 tCK
see
between Active Pulses + t + t
WL R
formula
tSH High Level Setup Time
0
to Active Read Strobe
t High Level Hold Time
HH
20
from Active Write Strobe
ns
ns
ns
ns
ns
ns
ns
ns
60 ns
60 ns
ns
ns
ns
ns
tR Rise Time
tF Fall Time
60 ns
60 ns
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5 Page 
SA3488
FUNCTIONAL OVERVIEW
The SA3488 is intended for large telephone switching systems, mainly central exchanges,
digital line concentrators and private branch exchanges where a distributed microcomputer
control approach is extensively used. It consists of a speech memory (SM), a control
memory (CM), a serial/parallel and a parallel/serial converter, an internal parallel bus,
an interface (8 data lines, 11 control signals) and dedicated logic. By means of repeated
clock division two time bases are generated. These are preset from an external
synchronization signal to two specific count numbers so that sequential scanning of the
bases give synchronous addresses to the memories and I/O channel controls. Different
preset count numbers are needed because of processing delays and data path direction.
The time-base for output channels is advanced with respect to the actual time. Each
serial PCM input channel is converted to parallel data and stored in the speech memory
at the beginning of any new time slot (according to first timebase) in the location
determined by input pin number and time slot number. The control memory CM
maintains the correspondences between input and output channels. More exactly, for
any output pin/output channel combination the control memory gives either the full
address of the speech memory location involved in the PCM transfer or an 8-bit word to
be supplied to the parallel/serial output converter. A 9th bit at each CM location defines
the data source for output links; low for SM, high for CM.
The late timebase is used to scan the output channels and to determine the pins to be
serviced within each channel. Enough idle cycles are left to the microprocessor for
synchronous instruction processing. Two 8-bit registers OR1 and OR2 supply feedback
data for control or diagnostic purposes; OR1 comes from the internal bus i.e. from
memories, while OR2 gives an opcode copy and additional data to the microcomputer.
A four byte, 5-bit stack register and an instruction register, under microcomputer control,
store input data available at the interface.
Dedicated logic, under control of the microprocessor interface, extracts the 0 channel
content of any selected PCM input bus, using spare cycles of SM.
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11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet SA3488.PDF ] | |
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