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PDF SA5225 Data sheet ( Hoja de datos )
| Número de pieza | SA5225 | |
| Descripción | Fiber optic postamplifier | |
| Fabricantes | Philips | |
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Hay una vista previa y un enlace de descarga de SA5225 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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INTEGRATED CIRCUITS
SA5225
Fiber optic postamplifier
Product specification
Replaces datasheet NE/SA5225 of 1997 Jun 05
IC19 Data Handbook
Philips
Semiconductors
1998 Oct 07
1 page  
Philips Semiconductors
Fiber optic postamplifier
Product specification
SA5225
NE5212
NE5224
CLOCK
RECOVERY
&
RETIMING
SD00376
Figure 3. Typical Fiber Optic Receiving System
INPUT BIASING
The DATA INPUT pins (4 and 5) are DC biased at approximately
2.9V by an internal reference generator. The SA5225 can be DC
coupled, but the driving source must operate within the allowable
1.4V to 4.4V input signal range (for VCC = 5V). If AC coupling is
used to remove any DC compatibility requirement, the coupling
capacitors C1 and C2 must be large enough to pass the lowest input
frequency of interest. For example, .001µF coupling capacitors
react with the internal 4.5k input bias resistors to yield a lower –3dB
frequency of 35kHz. This then sets a limit on the maximum number
of consecutive “1”s or “0”s that can be sensed accurately at the
system data rate. Capacitor tolerance and resistor variation (2.9k to
7.6k) must be included for an accurate calculation.
AUTO-ZERO CIRCUIT
Figure 5 also shows the essential details of the auto-zero circuit. A
feedback amplifier (A4) is used to cancel the offset voltage of the
forward signal path, so the input to the internal ECL comparator (A6)
is at its toggle point in the absence of any input signal. The time
constant of the cancelling circuitry is set by an external capacitor
(CAZ) connected between Pins 1 and 2. The formula for the lower
–3dB frequency is:
f*3dB
+
150
2p @ RAZ @ CAZ
where RAZ is the internal driving impedance which can vary from
155k to 423k over temperature and device fabrication limits. The
input coupling time constant must also be considered in determining
the lower frequency response of the SA5225.
INPUT SIGNAL LEVEL-DETECTION
The SA5225 allows for user programmable input signal
level-detection and can automatically disable the switching of its
ECL data outputs if the input is below a set threshold. This prevents
the outputs from reacting to noise in the absence of a valid input
signal, and insures that data will only be transmitted when the input
signal-to-noise ratio is sufficient for low bit-error-rate system
operation. Complimentary ECL flags (ST and STB) indicate whether
the input signal is above or below the desired threshold level.
Figure 6 shows a simplified block diagram of the SA5225
level-detect system. The input signal is amplified and rectified
before being compared to a programmable reference. A filter is
included to prevent noise spikes from triggering the level-detector.
This filter has a nominal 1µs time constant, and additional filtering
can be achieved by using an external capacitor (CF) from Pin 7 to
VCCA (the internal driving impedance is nominally 24k). The
resultant signal is then compared to a programmable level, VSET,
which is set by an internal voltage reference (2.64V) and an external
resistor divider (R1 and R2). The value of R1 + R2 should be
maintained at approximately 5k.
HYST
VTL
(OFF)
VTH
(ON)
Figure 4.
SD00377
The circuit is designed to operate accurately over a differential
2-12mVP-P square-wave input level detect range. This level,
VSET/100, is the average of VTH and VTL.
Nominal hysteresis of 3dB is provided by the complimentary ECL
output comparator yielding VTL
+
VSET
121
and
VTH
+
VSET
85 .
For
example, with VSET = 1.2V, a 14.05mVP-P square-wave differential
input will drive the ST pin high, and an input level below 9.95mVP-P
will drive the ST pin low.
Since a “JAM” function is provided (Pin 8) and can force the data
outputs to a predetermined state (DOUT = LOW, DOUT = HIGH), the
ST and JAM pins can be connected together to automatically
disable signal transmission when the chip senses that the input
signal is below the desired threshold. JAM (Pin 8) low enables the
Data Outputs. ST will be in a high ECL state for input signals below
threshold.
CAZ
1998 Oct 07
VBIAS
RAZ
250kΩ
RAZ
250kΩ
C1
DATA IN
C2
RIN
4.5kΩ
DIN
DINB
RIN
4.5kΩ
A1
–
+
A4
DOUT
A3 A6
DOUTB
ECL 10K
DATA OUT
SD00668
Figure 5. SA5225 Sample Application: Forward Gain Path Including Auto-Zero
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet SA5225.PDF ] | |
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