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PDF SA555D Data sheet ( Hoja de datos )
| Número de pieza | SA555D | |
| Descripción | Single Timer | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SA555D (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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LM555/NE555/SA555
Single Timer
www.fairchildsemi.com
Features
• High Current Drive Capability (200mA)
• Adjustable Duty Cycle
• Temperature Stability of 0.005%/°C
• Timing From µSec to Hours
• Turn off Time Less Than 2µSec
Applications
• Precision Timing
• Pulse Generation
• Time Delay Generation
• Sequential Timing
Description
The LM555/NE555/SA555 is a highly stable controller
capable of producing accurate timing pulses. With a
monostable operation, the time delay is controlled by one
external resistor and one capacitor. With an astable
operation, the frequency and duty cycle are accurately
controlled by two external resistors and one capacitor.
8-DIP
1
8-SOP
1
Internal Block Diagram
GND 1
R
Trigger 2
Comp.
RR
8 Vcc
Discharging Tr.
7 Discharge
Output 3
OutPut
Stage
F/F
Reset 4
Vref
Comp.
6 Threshold
Control
5
Voltage
©2002 Fairchild Semiconductor Corporation
Rev. 1.0.3
1 page  
LM555/NE555/SA555
Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls
below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's
internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor C1
and setting the flip-flop output at the same time.
The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t=RA*C and reaches 2Vcc/3
at td=1.1RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant RAC, the longer it takes
for the VC1 to reach 2Vcc/3. In other words, the time constant RAC controls the output pulse width.
When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop,
turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low.
In this way, the timer operating in the monostable repeats the above process. Figure 2 shows the time constant relationship
based on RA and C. Figure 3 shows the general waveforms during the monostable operation.
It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer
output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is
high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse
remains at below Vcc/3. Figure 4 shows such a timer output abnormality.
Figure 4. Waveforms of Monostable Operation (abnormal)
2. Astable Operation
+Vcc
4
RESET
2 TRIG
8
Vcc
DISCH 7
THRES 6
RA
RB
3 OUT
GND
CONT 5
C1
RL 1
C2
100
10
1
0.1
0.01
1E-3
100m
1
(RA+2RB)
10 100 1k
Fr equency(Hz)
10k 100k
Figure 5. Astable Circuit
Figure 6. Capacitance and Resistance vs. Frequency
5
5 Page 
Mechanical Dimensions
Package
6.40 ±0.20
0.252 ±0.008
#1 #8
8-DIP
LM555/NE555/SA555
Dimensions in millimeters
#4 #5
7.62
0.300
5.08
0.200
MAX
3.40 ±0.20
0.134 ±0.008
3.30 ±0.30
0.130 ±0.012
0.33
0.013
MIN
0~15°
0.25
+0.10
–0.05
0.010
+0.004
–0.002
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet SA555D.PDF ] | |
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