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PDF SA7016 Data sheet ( Hoja de datos )
| Número de pieza | SA7016 | |
| Descripción | 1.3GHz low voltage fractional-N synthesizer | |
| Fabricantes | Philips | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SA7016 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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INTEGRATED CIRCUITS
SA7016
1.3GHz low voltage fractional-N
synthesizer
Product specification
Supersedes data of 1999 Apr 20
1999 Nov 04
Philips
Semiconductors
1 page  
Philips Semiconductors
1.3GHz low voltage fractional-N synthesizer
Product specification
SA7016
CHARACTERISTICS
VDDCP = VDD = +3.0V, Tamb = +25°C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
Supply; pins 3, 9
VDD Digital supply voltage
VDDCP
Analog supply voltage
IDDTotal
Synthesizer operational total supply current
IStandby
Total supply current in power-down mode
RFin main divider input; pins 5, 6
VDDCP = VDD
VDD = +3.0V
logic levels 0 or VDD
2.7
2.7
–
–
fVCO
VRFin(rms)
VCO input frequency
AC-coupled input signal level
Rin (external) = Rs = 50Ω;
single-ended drive;
max. limit is indicative
@ 500 to 1300 MHz
350
–18
ZIRFin
Input impedance (real part)
CIRFin
Typical pin input capacitance
Nmain
Main divider ratio
fPCmax
Maximum loop comparison frequency
Reference divider input; pins 11, 12
fVCO = 1.2 GHz
fVCO = 1.2 GHz
indicative, not tested
–
–
512
–
fREFin
VRFin
Input frequency range from TCXO
AC-coupled input signal level
single-ended drive;
max. limit is indicative
5
360
ZREFin
Input impedance (real part)
CREFin
Typical pin input capacitance
RREF
Reference division ratio
Charge pump current setting resistor input; pin 10
fREF = 20 MHz
fREF = 20 MHz
–
–
4
RSET
External resistor from pin to ground
6
VSET
Regulated voltage at pin
RSET=7.5 kΩ
–
Charge pump outputs (including fractional compensation pump); pin 8; RSET =7.5kΩ, FC=80
ICP Charge pump current ratio to ISET1
Current gain IPH/ISET
–15
IMATCH
Sink-to-source current matching
VPH=1/2 VDDCP.
–10
IZOUT
Output current variation versus VPH2
VPH in compliance range
–10
ILPH Charge pump off leakage current
VPH=1/2 VCC
–10
VPH Charge pump voltage compliance
0.7
TYP.
–
–
6.2
1
–
–
MAX.
UNIT
5.5
5.5
7.3
TBD
V
V
mA
µA
1300
0
MHz
dBm
625 – Ω
1.0 – pF
– 65535
– 4 MHz
– 40 MHz
–
1300
mVPP
10 – kΩ
1.0 – pF
– 1023
7.5 15 kΩ
1.25 – V
+15 %
+10 %
+10 %
+10 nA
– VDDCP–0.8 V
1999 Nov 04
5
5 Page 
Philips Semiconductors
1.3GHz low voltage fractional-N synthesizer
Product specification
SA7016
Serial programming bus
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 8
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the
Serial bus timing characteristics. See Figure 8.
VDD = VDDCP =+3.0V; Tamb = +25°C unless otherwise specified.
SYMBOL
PARAMETER
Serial programming clock; CLK
tr Input rise time
tf Input fall time
Tcy Clock period
Enable programming; STROBE
tSTART
tW
tSU;E
Delay to rising clock edge
Minimum inactive pulse width
Enable set-up time to next clock edge
Register serial input data; DATA
tSU;DAT
tHD;DAT
Input data to clock set-up time
Input data to clock hold time
data is latched into different working registers or temporary
registers. In order to fully program the synthesizer, 3 words must be
sent: C, B, and A. Table 1 shows the format and the contents of
each word. The D word is normally used for testing purposes. When
sending the B-word, data bits FC7–0 for the fractional compensation
DAC are not loaded immediately. Instead they are stored in
temporary registers. Only when the A-word is loaded, these
temporary registers are loaded together with the main divider ratio.
MIN.
–
–
100
40
1/fCOMP
20
20
20
TYP.
10
10
–
–
–
–
–
–
MAX.
40
40
–
–
–
–
–
–
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
Application information
CLK
tSU;DAT
Tcy
tHD;DAT
tr tf
tSU;E
DATA
ADDRESS
MSB
LSB
STROBE
tSTART
Figure 8. Serial Bus Timing Diagram
tw
SR01417
1999 Nov 04
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SA7016.PDF ] | |
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