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SA702D PDF даташит

Спецификация SA702D изготовлена ​​​​«Philips» и имеет функцию, называемую «Divide by: 64/65/72 triple modulus low power ECL prescaler».

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Номер произв SA702D
Описание Divide by: 64/65/72 triple modulus low power ECL prescaler
Производители Philips
логотип Philips логотип 

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SA702D Даташит, Описание, Даташиты
Philips Semiconductors RF Communications Products
Divide by: 64/65/72 triple modulus low power
ECL prescaler
Product specification
SA702
DESCRIPTION
The SA702 triple modulus (Divide By
64/65/72) low power ECL prescaler is used in
synthesizer systems to achieve low phase
lock time, broad operating range, high
reference frequency and small frequency
step sizes. The minimum supply voltage is
2.7V and is compatible with the CMOS
UMA1005 synthesizer from Philips and other
logic circuits. The low supply current allows
application in battery operated low-power
equipment. Maximum input signal frequency
is 1.1GHz for cellular and other land mobile
applications. There is no lower frequency
limit due to a fully static design. The circuit is
implemented in ECL technology on the
QUBiC process. The circuit will be available
in an 8-pin SO package with 150 mil package
width and in 8-pin dual in-line plastic
package.
FEATURES
Low voltage operation
Low current consumption
Operation up to 1.1GHz
ESD hardened
APPLICATIONS
Cellular phones
Cordless phones
RF LANs
Test and measurement
Military radio
VHF/UHF mobile radio
VHF/UHF hand-held radio
PIN CONFIGURATION
N, D Package
IN 1
VC 2
MCC2 3
OUT 4
8 IN
7 GND
6 MC1
5 OUT
ORDERING INFORMATION
DESCRIPTION
8-Pin Plastic Dual In-Line Package (DIP)
8-Pin Plastic Small Outline (SO) package (Surface-mount)
TEMPERATURE RANGE
-40 to +85°C
-40 to +85°C
ORDER CODE
SA702N
SA702D
DWG #
0404B
0174C
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
VCC
VIN
IO
TSTG
TA
θJA
Supply voltage
Voltage applied to any other pin
Output current
Storage temperature range
Operating ambient temperature range
Thermal impedance
D package
N package
RATING
-0.3 to +7.0
-0.3 to (VCC + 0.3)
10
-65 to +125
-55 to +125
158
108
UNITS
V
V
mA
°C
°C
°C/W
June 17, 1993
2 853-1709 10044









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SA702D Даташит, Описание, Даташиты
Philips Semiconductors RF Communications Products
Divide by: 64/65/72 triple modulus low power
ECL prescaler
BLOCK DIAGRAM
Product specification
SA702
QQ
D
QQ
D
Q
D
Q
D
Q
D
Q
D
Q
D
QQ
D
June 17, 1993
3









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SA702D Даташит, Описание, Даташиты
Philips Semiconductors RF Communications Products
Divide by: 64/65/72 triple modulus low power
ECL prescaler
Product specification
SA702
DC ELECTRICAL CHARACTERISTICS
The following DC specifications are valid for TA = 25°C and VCC = 3.0V; unless otherwise stated. Test circuit Figure 1.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
MIN TYP
VCC Power supply voltage range
ICC Supply current
VOH Output high level
VOL Output low level
VIH MC1 input high threshold
VIL MC1 input low threshold
VIH MC2 input high threshold
VIL MC2 input low threshold
IIH MC1 input high current
IIL MC1 input low current
IIH MC2 input high current
IIL MC2 input low current
fIN = 1GHz, input level = 0dBm
No load
IOUT = 1.2mA
VMC1 = VCC = 6V
VMC1 = 0V, VCC = 6V
VMC2 = VCC = 6V
VMC2 = 0V, VCC = 6V
2.7
VCC-1.4
2.0
–0.3
2.0
–0.3
–100
–100
4.5
VCC-2.6
0.1
–30
0.1
–30
MAX
6.0
VCC
0.8
VCC
0.8
50
50
UNITS
V
mA
V
V
V
V
V
V
µA
µA
µA
µA
AC ELECTRICAL CHARACTERISTICS
These AC specifications are valid for fIN = 1GHz, input level = 0dBm, VCC = 3.0V and TA = 25°C; unless otherwise stated. Test circuit Fig. 1.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
VIN Input signal amplitude1
fIN Input signal frequency
1000pF input coupling
Direct coupled input2
1000pF input coupling
MIN
0.05
0
TYP
MAX
2.0
1.1
1.1
VP-P
GHz
GHz
RID Differential input resistance
VO Output voltage
tS Modulus set-up time1
tH Modulus hold time1
tPD Propagation time
DC measurement
VCC = 5.0V
VCC = 3.0V
5 k
1.6 VP-P
1.2 VP-P
5 ns
0 ns
10 ns
NOTES:
1. Maximum limit is not tested, however, it is guaranteed by design and characterization.
2. For fIN < 50MHz, minimum input slew rate of 32V/µs is required.
DESCRIPTION OF OPERATION
The SA702 comprises a frequency divider
circuit implemented using a divide by 4 or 5
synchronous prescaler followed by a 5 stage
synchronous counter, see BLOCK
DIAGRAM. The normal operating mode is for
MC1 (Modulus Control) to be set high and
MC2 input to be set low in which case the
circuit comprises a divide by 64. For divide
by 65 the MC1 singal is forced low, causing
the prescaler circuit to switch into divide by 5
operation for the last cycle of the
synchronous counter. For divide by 72, MC2
is set high configuring the prescaler to divide
by 4 and the counter to divide by 18. A truth
table for the modulus values is given below:
Table 1.
Modulus
64
65
72
72
MC1
1
0
0
1
MC2
0
0
1
1
For minimization of propagation delay effects,
the second divider circuit is synchronous to
the divide by 4/5 stage output.
The prescaler input is positive edge sensitive,
and the output at the final count is a falling
edge with propagation delay tPD relative to
the input. The rising edge of the output
occurs at the count 32 with delay tPD.
The MC1 and MC2 inputs are TTL
compatible threshold inputs operating at a
reduced input current. CMOS and low
voltage interface capability are allowed.
The prescaler input is differential and ECL
compatible. The output is differential ECL
compatible.
June 17, 1993
4










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