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PDF SA8016DH Data sheet ( Hoja de datos )
| Número de pieza | SA8016DH | |
| Descripción | 2.5GHz low voltage fractional-N synthesizer | |
| Fabricantes | Philips | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SA8016DH (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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INTEGRATED CIRCUITS
SA8016
2.5GHz low voltage fractional-N
synthesizer
Product specification
Supersedes data of 1999 Apr 16
1999 Nov 04
Philips
Semiconductors
1 page  
Philips Semiconductors
2.5GHz low voltage fractional-N synthesizer
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
VDD
VDDCP
∆VDDCP–VDD
Vn
V1
∆VGND
Digital supply voltage
Analog supply voltage
Difference in voltage between VDDCP and VDD (VDDCP ≥ VDD)
Voltage at pins 1, 2, 5, 6, 11 to 16
Voltage at pin 8, 9
Difference in voltage between GNDCP and GND (these pins should be
connected together)
Tstg
Tamb
Tj
Storage temperature
Operating ambient temperature
Maximum junction temperature
Handling
Inputs and outputs are protected against electrostatic discharge in
normal handling. However, to be totally safe, it is desirable to take
normal precautions appropriate to handling MOS devices.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
Rth j–a
Thermal resistance from junction to ambient in free air
Product specification
SA8016
MIN.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–55
–40
MAX.
+5.5
+5.5
+2.8
VDD + 0.3
VDDCP + 0.3
+0.3
UNIT
V
V
V
V
V
V
+125
+85
150
°C
°C
°C
VALUE
120
UNIT
K/W
1999 Nov 04
5
5 Page 
Philips Semiconductors
2.5GHz low voltage fractional-N synthesizer
Product specification
SA8016
Charge pump currents
CP0
IPHP
IPHP–SU
0
3xISET
15xlSET
1
1xlSET
5xlSET
NOTES:
1. ISET=VSET/RSET bias current for charge pumps.
2. IPHP–SU is the total current at pin PHP during speed up condition.
Lock Detect
The output LOCK maintains a logic ‘1’ when the auxiliary phase
detector ANDed with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than "1 period of the
frequency at the input REFin+, –. One counter can fulfill the lock
condition when the other counter is powered down. Out of lock (logic
‘0’) is indicated when both counters are powered down.
Power-down mode
The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits in
B-word. If PON = 0, then the part is powered up when PD = 1. PON
can be used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after power-down, the main and reference
dividers are synchronized to avoid possibility of random phase
errors on power-up.
1999 Nov 04
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet SA8016DH.PDF ] | |
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