|
|
PDF SA9101 Data sheet ( Hoja de datos )
| Número de pieza | SA9101 | |
| Descripción | PCM FRAME ALIGNER | |
| Fabricantes | Sames | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de SA9101 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
sames
SA9101
PCM FRAME ALIGNER
FEATURES
n Frame alignment/synthesis for PCM30 n Error counters for code errors
double frame and CRC-multiframe
format.
(switchable to "S zeros counter"), frame
i
errors and CRC4 errors
n Meets CCITT Rec.G704
n Sub-multiframe assigned CRC Error
indication with possibility of automatic
n Interface to route selectable between
insertion in Si-bit position of outgoing
HDB3 and fibre optical
multiframe.
n HDB3 outputs switchable between fully n Simplified data transfer between
bauded and half bauded format
SA9101 and controller, supported by
n Error checking via CRC4 procedure
data stacks for receive and transmit
signalling data, selectable interrupt-
n Insertion and extraction of alarms and
sources and DMA facilities.
facility signals
n Double frame marker for serial data
n Selectable system - clock (4096 kHz/
extraction support
8192 kHz)
n Repeated transmission of signalling
n Selectable Interface mode (2048/4096
data, if not updated.
kBit/s) to system internal highway
n Three transparent modes for timeslot 0
n Programmable offsets for receive and
in transmit direction
transmit data
n Transparent mode for receive direction
n Two frame receive buffer for receive n HDB3 error indication
route clock wander and jitter n Idle channel data insertion selectable
compensation
for any timeslot
n
Slip detection and direction indication
n
Channel loopback capabilities, test and
diagnostic capabilities
n Extended HDB3 error detection
n Parity checks
DESCRIPTION:
The SA9101 (Frame Alignment unit for PCM30 Systems) is a C-MOS device which
implements the interface to PCM30 Transmission Systems.
In the receive direction, the device performs HDB3 decoding, Frame alignment
(selectable between doubleframe and CRC-Multiframe) and extraction of signalling
data.
Wander absorption between the PCM carrier and the system internal highway is
performed using an internal 2 frame memory. The incoming data stream is monitor1e/4d0
aMn71d-1797
PDS039-SA9101-001
REV.A
09-09-94
1 page  
SA9101
PIN DESCRIPTION
Pin Name Direction
AINT/DFPY
ACKNLQ
A[3-0]
CEQ
CHPAR/DFM
O
I
I
I
O
COS
DRA
DRB
DRO
DXA
DXB
DXI
D[7-0]
OPIN
OPOUT
RCAS/RREQ
I
I
I
O
O
O
I
B
I
O
O
RCLK
RDQ
RESQ
RFSPQ
I
I
I
O
SCLK
SYPQ
TCAS/XREQ
I
I
O
VDD
V
SS
WRQ
XCHPAR
XRCLK
XTOM
XTOP
S
S
I
O
O
O
O
Pin No.
DIL PLCC
35
32 36
19-16 21-18
22 26
46
23
27
26
2
38
39
30
14-7
29
6
35
27
31
30
4
42
43
34
16-9
33
8
39
25 29
20 22
31 35
57
24 28
28 32
36 40
15 17
34 38
21 25
33 37
37 41
13
40 44
Description
Alarm interrupt/Double Frame Parity
DMA Acknowledge
Address Bus
Chip Enable
Receive Channel Parity/
Double Frame Marker
Carrier out of Service
Receive Data in Plus
Receive Data in Minus
Receive Data Out
Transmit Data Out Plus
Transmit Data Out Minus
Transmit Data In
Data Bus
Receive Optical Interface Data
Transmit Optical Interface Data
Receive TS16 Signal/Receive DMA
Interrupt Request
Receive Route Clock
Read Enable
Reset
Receive Frame Synchronisation
Pulse
System Clock
Synchronisation Pulse
Transmit TS16 Signal/Transmit DMA
Interrupt Request
+5V Supply
0V Ground
Write Enable
Transmit Channel Parity
Transmit Route Clock
Test Data Output Minus
Test Data Output Plus
sames
5/40
5 Page 
SA9101
Figure 1.0 illustrates the operation of the receive Speech Memory:
A slip condition is detected when the Write Pointer (W) and the Read pointer (R) of the
memory are nearly coincident, i.e. the Write pointer is within the Slip Limits (S+, S-). If
a slip condition is detected, a negative slip ( the next received frame is skipped) or a
positive slip (the previous received frame is read out twice) is performed at the System
Interface, depending on the difference between RCLK and SCLK, i.e. on the position of
pointer R and W within the memory.
To reduce delay, the Receive Speech Memory can be switched to one frame length. For
correct operation, System Clock SCLK and Synchronization Pulse SYPQ have to be
derived from the Receive Route Clock RCLK and the Receive Frame Synchronous Pulse
RFSPQ (PLL application). In Single Frame Mode, however, it is not possible to perform
a slip after the slip condition has been detected.
Receive Transparent Mode
If enabled, the frame aligner does not try to synchronise on the received data if
synchronisation is lost. The AIS to the System Interface is disabled. The data appears
on the System Interface synchronised to the System Clock (SCLK) as received.
Transmit path
The PCM data is received from the system internal highway at port DXI at 2048 kbps or
4096 kbps. The channel assignment is equivalent to the receive direction. Data in invalid
timeslots will be ignored.
Latching of data is controlled by the System Clock (SCLK) and the Synchronization Pulse
(SYPQ), in conjunction with the programmed offset values of the Transmit Timeslot/
Clockslot Counters.
The Transmit Route Clock (XRCLK) is derived directly from the system clock by an
internal clock divider. Consequently, the data received from the system interface is
switched through without the need of intermediate storage.
The parity generation/checking mechanism is symmetrical to the receive path. The
channel data is checked with the channel parity information generated internally or
externally (input at port XCHPAR with selectable parity type). Errors are reported to the
microprocessor interface. To avoid difficulties with external parity generation, the parity
signal for non-speech data (TS0 and TS16) is ignored.
Transmitter
The serial bit stream is then processed by the transmitter which has the following
functions:
- Frame/multiframe synthesis of one of the selectable framing formats
- Insertion of service and data link information.
- Remote Alarm generation
- CRC generation and insertion of CRC bits
sames
11/40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SA9101.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SA910 | Variable gain RF predriver amplifier |  Philips |
| SA9101 | PCM FRAME ALIGNER | Sames |
| SA9102C | SINGLE PHASE UNIDIRECTIONAL POWER/ENERGY METERING IC PULSE OUTPUT | Sames |
| SA9102CPA | SINGLE PHASE UNIDIRECTIONAL POWER/ENERGY METERING IC PULSE OUTPUT | Sames |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |