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PDF SAA2502 Data sheet ( Hoja de datos )
| Número de pieza | SAA2502 | |
| Descripción | ISO/MPEG Audio Source Decoder | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
SAA2502
ISO/MPEG Audio Source Decoder
Preliminary specification
Supersedes data of 1997 Apr 18
File under Integrated Circuits, IC01
1997 Nov 17
1 page  
Philips Semiconductors
ISO/MPEG Audio Source Decoder
6 PINNING
SYMBOL
FSCLK
SCK
SD
WS
TRST
SPDIF
CCLK
CDATA
CMODE
INT
RESET
STOP
CDRQ
CDCL
CD
GND1
CDEF
VDD1
CDSY
CDVAL
TMS
REFCLK
PHDIF
TCK
FSCLKIN
X22IN
X22OUT
GND2
MCLK24
VDD2
MCLKOUT
MCLKIN
TDI
RGTPOS
RGTNEG
REFN
REFP
LFTNEG
LFTPOS
TC0
1997 Nov 17
PIN DESCRIPTION
1 sample rate clock output; buffered signal
2 baseband audio data I2S clock output
3 baseband audio I2S data output
4 baseband audio data I2S word select output
5 boundary scan test reset input
6 SPDIF baseband audio output
7 L3 clock/I2C-bus bit clock input
8 L3 data/I2C-bus serial data input/output; note 1
9 L3 mode (address/data select input)
10 interrupt request output; active LOW; note 1
11 master reset input
12 soft reset/stop decoding input
13 coded data request output
14 coded data bit clock input/output; note 2
15 MPEG coded data input
16 ground 1
17 coded data error flag input
18 supply voltage 1
19 coded data byte or frame sync input
20 coded data valid flag input
21 boundary scan test mode select input
22 PLL reference clock input
23 PLL phase comparator output; note 2
24 boundary scan test clock input
25 sample rate clock input
26 22.579 MHz clock oscillator input or signal input
27 22.579 MHz clock oscillator output
28 ground 2
29 master clock frequency indication input
30 supply voltage 2
31 master clock oscillator output
32 master clock oscillator input or signal input
33 boundary scan test data input
34 analog right channel positive output
35 analog right channel negative output
36 low reference voltage input for analog outputs
37 high reference voltage input for analog outputs
38 analog left channel negative output
39 analog left channel positive output
40 factory test scan chain control 0 input
5
Preliminary specification
SAA2502
5 Page 
Philips Semiconductors
ISO/MPEG Audio Source Decoder
Preliminary specification
SAA2502
7.2.4
LIMITED SAMPLING FREQUENCY SUPPORT FOR
INTERNAL SAMPLING CLOCKS
7.2.4.1 When sampling frequency is limited to
44.1 and/or 22.05 kHz:
In this event MCLKIN is only required to generate the
master clock frequency. Consequently the remarks on
MCLKIN frequency also apply in this special case.
7.2.4.2 When sampling frequency is limited to
48, 32, 24 and/or 16 kHz:
In this event X22IN is not required. Therefore X22IN
should be connected to VSS or VDD, but it is more efficient
to apply any available clock signal to X22IN. Because
44.1 kHz is the default initial sampling frequency it may
also be advisable to over-rule the sampling frequency after
a hard reset.
7.3 Input interface module
The input interface module handles the reception of the
coded input data stream.
The module can be configured to operate in 3 distinct
modes of operation:
• The master input mode
• The slave input mode
• The buffer controlled input mode.
Input interface mode must be stationary while the device is
in normal operation. Changing mode will result in an
(automatically generated) internal soft reset.
The inputs CD, CDVAL, CDEF and CDSY are all clocked
at the rising edge of the CDCL bit clock.
CDRQ changes at the falling edge of CDCL.
CDVAL = logic 0 indicates that CD and CDEF should be
ignored while CDVAL = logic 1 indicates that CD is a valid
coded input stream data bit (CDEF is then its error
attribute).
CDEF = logic 0 means that the value of CD may be
assumed to be reliable while CDEF = logic 1 means that
the value of CD is flagged as insecure (e.g. due to erratic
non-correctable channel behaviour). The value of CDEF
may be different for each data bit, but is combined by the
SAA2502 for every group of 8 (byte aligned) valid coded
input bits.
CDSY will only have effect when the SYMOD control flags
are set to 10 or 11. When SYMOD = 10 the valid input bit
at a rising edge of CDSY marks the start of a new byte
(when SYMOD = 11 it marks the start of a new MPEG
audio frame). Note that just the rising edge of CDSY is
important, the falling edge has no meaning.
If CDSY is used with SYMOD = 10 leading edges must be
frequent enough to assure fast byte alignment, if used with
SYMOD = 11 a leading edge must be present every frame.
Leading edges of CDSY may occur while CDVAL is
(implicitly) high. Alternatively, a situation as shown in Fig.8
is also allowed, where CDSY has a rising edge while
CDVAL is low, i.e. during invalid data. The first valid CD bit
after the rising edge of CDVAL is then interpreted as the
first byte or frame bit.
The output pin CDRQ is used to request new coded input
data.
Table 4 Signals of coded data input interface
SIGNAL
CD
CDVAL
CDEF
CDSY
CDCL
CDRQ
DIRECTION
input
input
input
input
input/output
output
FUNCTION
coded data input bit
coded data bit valid flag
coded data bit error flag
coded data sync (start of byte/frame) indication
coded data bit clock
coded data request
1997 Nov 17
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAA2502.PDF ] | |
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