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PDF SAA2521GP Data sheet ( Hoja de datos )
| Número de pieza | SAA2521GP | |
| Descripción | Masking threshold processor for MPEG layer 1 audio compression applications | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
SAA2521
Masking threshold processor for
MPEG layer 1 audio compression
applications
Preliminary specification
File under Integrated Circuits, IC01
August 1993
1 page  
Philips Semiconductors
Masking threshold processor for MPEG
layer 1 audio compression applications
Preliminary specification
SAA2521
PINNING
SYMBOL
LTCNT1
LTCNT0
LTENA
LTCLK
LTDATA
VSS
LTCNT1C
LTCNT0C
LTENC
LTCLKC
LTDATAC
TEST1
TEST2
VDD
TEST3
TEST4
TEST5
TEST6
TEST7
NODONE
RESOL0
RESOL1
RESET
VDD
VSS
CLK24
TEST8
TEST9
TEST10
PWRDWN
SWS
SCL
FDAC
FDAF
FSYNC
FRESET
FDIR
SCALE
FS256
VDD
August 1993
PIN DESCRIPTION
1 mode control 1, microcontroller interface input
2 mode control 0, microcontroller interface input
3 enable microcontroller interface input
4 bit clock microcontroller interface input
5 data, microcontroller interface (3-state inputs/outputs)
6 supply ground (0 V)
7 control 1; microcomputer interface
8 control 0; microcomputer interface
9 enable microcontroller interface
10 bit clock; microcontroller interface
11 data; microcontroller interface, (3-state inputs/outputs)
12 test output; do not connect
13 test output; do not connect
14 positive supply voltage (+ 5 V)
15 test mode input; to be connected to VDD
16 test mode input; to be connected to VDD
17 test input; to be connected to VSS
18 test input; to be connected to VSS
19 test input; to be connected to VSS
20 no done state selection input
21 resolution selection 0 input
22 resolution selection 1 input
23 active HIGH reset input
24 positive supply voltage (+ 5 V)
25 supply ground (0 V)
26 24.576 MHz processing clock input
27 test input; to be connected to VSS
28 test input; to be connected to VSS
29 test input; to be connected to VSS
30 power-down input
31 word selection input; (Filtered) - I2S-interface
32 bit clock input; (Filtered) - I2S-interface
33 filtered data (Filtered) - I2S-interface (3-state inputs/outputs)
34 filtered data (Filtered) - I2S-interface (3-state inputs/outputs)
35 sub-band synchronization on (Filtered) - I2S-interface, input
36 reset signal input from SAA2520
37 direction of the I2S-interface; input
38 scale factor index select (note 1)
39 system clock input; sample frequency × 256
40 positive supply voltage (+ 5 V)
5
TYPE
I
I
I
I
I/O
O
O
O
O
I/O
I
I
I
I
I
I
I
I
I/O
I/O
I
I
I
I
I
5 Page 
Philips Semiconductors
Masking threshold processor for MPEG
layer 1 audio compression applications
Preliminary specification
SAA2521
SCL
output
input
4T
t cH t cL
t d4
t d3
t su1
t h1
MBC127 - 2
OUTPUT applies to FDAF and FDAC in the output mode.
INPUT applies to FDAF and FDAC in the input mode, SWS and FSYNC.
T = one Fs256 cycle time
tcH ≥ T + 35 ns minimum HIGH time SCL
TcL ≥ T + 35 ns minimum LOW time SCL
td3 ≥ 2T − 10 ns hold time output after SCL HIGH
td4 ≤ 3T + 60 ns delay time output after SCL HIGH
ts1 ≥ 20 ns set-up time input before SCL HIGH
th1 ≥ T + 35 ns hold time input after SCL HIGH
FDIR
FDA
t W1
HIGH Z
t W2
HIGH Z
MEA692 - 1
tw1 ≥ 3T minimum time high impedance to FDA enabled
tw2 ≥ 2T + 35 ns maximum time FDA enabled to high impedance
Fig.8 (Filtered) - I2S-interface timing.
August 1993
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet SAA2521GP.PDF ] | |
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