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Número de pieza | SAA4700T | |
Descripción | VPS dataline processor | |
Fabricantes | Philips | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de SAA4700T (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
No Preview Available ! INTEGRATED CIRCUITS
DATA SHEET
SAA4700T
VPS dataline processor
Preliminary specification
File under Integrated Circuits, IC02
March 1991
1 page Philips Semiconductors
VPS dataline processor
Preliminary specification
SAA4700T
Composite sync output (CSO)
A composite sync output signal for customer application is
provided (pin 6).
DAV output
The data available output pin 13 is set LOW after an error
free data line 16 is received. DAV returnes to HIGH after
the beginning of the next first field. If no valid data is
available DAV remains HIGH.
A short duration pulse of 1 µs (Fig.5) is inserted at the
beginning of dataline 16; it will ensure that a HIGH-to-LOW
transmission occurs which can then be used for triggering.
5 MHz VCO and phase detector
The resistor connected between pin 15 and VP2
determines the current into the voltage controlled
oscillator. The RC network connected to pin 19 acts as a
low-pass filter for the phase detector.
Power supply
To prevent crosscoupling the circuit is provided with
separate ground and supply pins for analog and digital
parts (pins 3, 4, 17 and 18).
Table 1 Information per word in dataline 16
WORD NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CONTENT
run in
start code
program source identification (binary coded)
program source identification (ASCII sequential)
sound and VTR control information
program/test picture identification
internal information exchange
address assignment of signal distribution
messages/commands
VTR control / information
reserve
March 1991
5
5 Page Philips Semiconductors
VPS dataline processor
Preliminary specification
SAA4700T
handbook, full pagewidth
VP +5 V
22 4.7
nF 8.2 kΩ nF
n.c.
20 19 18
0.1 µF
17 16
75 kΩ
(2%)
n.c.
DAV
15 14 13 12
11
SAA4700T
1 2 3 4 5 6 7 8 9 10
1 nF
4.7
nF
0.1
µF n.c.
470
4.7 kΩ pF
CSO
SCL SDA
CVBS
MEH136
Fig.6 Application circuit.
I2C-BUS FORMAT
S SLAVE ADDRESS
A DATA
A DATA
A DATA
A DATA
A DATA
P
S
SLAVE ADDRESS
A
DATA
P
= start condition
= 0010 0001 or 0010 0011 for set input AD = HIGH respectively LOW on pin 8
(the circuit is only a slave transmitter)
= acknowledge, generated by the slave or the master
= five data bytes, see words in Table 1
= stop condition respectively non-acknowledge by the microcontroller
Remarks to I2C-bus transmission
• the MSB of each word is transmitted first
• there is no restriction on the number of words to be transmitted, but if more than five words are requested, the following
content will be “FF” continuously.
• Normally every dataline transmission has to be ended with STOP condition by non-acknowledge of the controller.
March 1991
11
11 Page |
Páginas | Total 14 Páginas | |
PDF Descargar | [ Datasheet SAA4700T.PDF ] |
Número de pieza | Descripción | Fabricantes |
SAA4700 | VPS dataline processor | Philips |
SAA4700T | VPS dataline processor | Philips |
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