PDF SAA4981 Data sheet ( Hoja de datos )

Número de pieza	SAA4981
Descripción	Monolithic integrated 16 : 9 compressor
Fabricantes	Philips
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET SAA4981 Monolithic integrated 16 : 9 compressor Preliminary speciﬁcation Supersedes data of May 1994 File under Integrated Circuits, IC02 1995 Oct 05 1 page Philips Semiconductors Monolithic integrated 16 : 9 compressor Preliminary speciﬁcation SAA4981 FUNCTIONAL DESCRIPTION Applicable video standards The integrated 16 : 9 compressor can be used for the following video standards; B, C, D, G, H, I, K, K1, L, M and N. standards D, I, K, K1 and L will show a reduced video bandwidth above 5 MHz. Clamping circuit The clamping circuits clamp the video input signals Y, (B−Y) and (R−Y) to the DC level of the clamp reference signal fed from the clamp reference circuit. This is necessary to ensure that the input signals are in the correct input voltage range for the 5 MHz low-pass filters and the SC line memories. Internal pre ﬁlters Before the signals are sampled in the time discrete and amplitude continuous area, low-pass filtering is necessary to avoid any aliasing. Even if the inputs have already been low-pass filtered further filtering is advantageous for the electromagnetic compatibility (EMC). The same transfer function is used for all three low-pass filters because of the same bandwidth for the luminance and chrominance signals (up to 5 MHz). SC line memories After the low-pass filters the input signals are fed to the SC line memories. The signals are sampled at a clock frequency of 13.5 MHz. One video line later the signals are read with a clock frequency of 18 MHz in the compression mode. The result of the different clock frequencies is a horizontal compression by a factor of 4⁄3. The clocks and the horizontal starting pulses for the SC line memories are fed from the controller. Two line memories are required for each signal path because in the compression mode, in one video line the signals are sampled to the SC line memories with 13.5 MHz and one video line later the signals are read with 18 MHz. In the bypass mode, via the SC line memories, in one video line the signals are sampled with 13.5 MHz and one video line later the signals are read with 13.5 MHz. The SC line memories are suitable for signals with a bandwidth up to 5 MHz. With a multiplexer (MUX) behind the SC line memories, the sampled video signal is connected to the internal post filters. Output multiplexer MUX Y, MUX (B−Y) and MUX (R−Y) The output multiplexers are controlled via C1 and C2 fed from the controller. The multiplexers are used to connect one of the four input signals to the output and, also, enable fast switching. The input signals of the multiplexers for one component [Y, (B−Y) or (R−Y)] are as follows: • The output signal of the post filter • The uncompressed signal after the input clamping • The clamping reference signal • The signal for the side panel determined by YSIDE, BYSIDE and RYSIDE. The horizontal separation circuit The 54 MHz horizontal PLL is locked to the positive edge of the digital HREF signal, which is generated in the horizontal separation circuit. It is also possible to use the positive edge of the burst key of a sandcastle signal. 54 MHz horizontal PLL The 13.5 MHz clock frequency for the sampling clock and the 18 MHz clock frequency for the reading clock are generated in the 54 MHz horizontal PLL. The 13.5 MHz clock and the 18 MHz clock are line locked. Clamp reference Reference voltages are generated In the clamp reference block. These DC signals are used in the clamping circuits as input signals for the output multiplexers and as reference voltages for the SC line memories. Four external capacitors at the pins CLMY, CLMBY, CLMRY and BGREF respectively are necessary to provide smoothing for the reference voltages. A black level reference signal is available at CLAOUT. 1995 Oct 05 5 5 Page Philips Semiconductors Monolithic integrated 16 : 9 compressor Preliminary speciﬁcation SAA4981 SYMBOL PARAMETER Compressed video; note 2 GY8 GY9 GY10 GY11 GY12 GY13 AYpre YOUT/YIN at input frequency YOUT/YIN at input frequency YOUT/YIN at input frequency YOUT/YIN at input frequency YOUT/YIN at input frequency YOUT/YIN at input frequency pre ﬁlter stop-band characteristic, damping factor for input signals AYpost post ﬁlter stop-band characteristic, damping factor for input signals (B−Y)OUT RO(U) VoU(p-p) S/N output resistance output voltage (peak-to-peak value) signal-to-noise ratio FPN(p-p) ﬁxed pattern noise peak-to-peak referenced to 1.33 V (p-p) video αctU crosstalk between different inputs \|td\| delay between different outputs td jitter in output signal to input HREF signal Bypass not via the SC line memories GU1 frequency response GU2 frequency response Bypass via the SC line memories; note 2 GU3 (B−Y)OUT/(B−Y)IN at input frequency GU4 (B−Y)OUT/(B−Y)IN at input frequency GU5 (B−Y)OUT/(B−Y)IN at input frequency GU6 (B−Y)OUT/(B−Y)IN at input frequency GU7 (B−Y)OUT/(B−Y)IN at input frequency CONDITIONS fi = 1 MHz; fo = 1.3 MHz fi = 2 MHz; fo = 2.7 MHz fi = 3 MHz; fo = 4 MHz fi = 3.75 MHz; fo = 5 MHz fi = 4 MHz; fo = 5.3 MHz fi = 5 MHz; fo = 6.67 MHz fi > 10 MHz fi > 20 MHz fi > 100 MHz fi > 14 MHz fi > 20 MHz fi > 100 MHz 1.33 V (p-p)/Veff noise; unweighted; fi = 200 kHz to 5 MHz fclk < 5 MHz fi = 1 MHz fripple = 0 to 4 MHz attenuation at 5 MHz compared to 1 MHz fi = 1 MHz fi = 2 MHz fi = 3 MHz fi = 4 MHz fi = 5 MHz MIN. TYP. MAX. UNIT −1 − −1 − −2 − −3 − −4 − −6 − 20 − 32 − 42 − 20 − 32 − 40 − +1 dB +1 dB 0 dB −1 dB −1 dB −1 dB − dB − dB − dB − dB − dB − dB − − 100 Ω − 1.33 2.1 V 54 − − dB 42 − 40 − −− −− − dB − dB 30 ns 10 ns −0.5 − 0− +0.5 dB −2 dB −1.1 − −1.3 − −1.7 − −2.3 − −3.1 − +0.9 +0.7 +0.3 −0.3 −1.1 dB dB dB dB dB 1995 Oct 05 11 11 Page

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