|
|
PDF SED1521 Data sheet ( Hoja de datos )
| Número de pieza | SED1521 | |
| Descripción | DOT MATRIX LCD DRIVER | |
| Fabricantes | ETC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de SED1521 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
SED1520/21
DOT MATRIX LCD DRIVER
S-MOS Systems, Inc.
October, 1996
Version 1.0 (Preliminary)
371-1.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 1
1 page  
1.0 General Description
1.0 – 1.2
1.0 GENERAL DESCRIPTION
1.1 DESCRIPTION
The SED1520 is a dot matrix LCD driver LSI intended for display of characters and graphics. The
bit-addressable display data, which is sent from a microcomputer, is stored in a built-in display data
RAM and generates the LCD drive signal.
The SED1520 incorporates innovative circuit design strategies to assure very low current dissipa-
tion and a wide range of operating voltages. With these features, the SED1520 permits the user to
implement high-performance handy systems operating from a miniature battery.
In order for the user to adaptively configure his system, the SED1520 family offers two application
forms. One form allows an LCD display of 12 characters × 2 lines with an indicator with a single
chip. The other is dedicated to driving a total of 80 segments, enabling a medium-size display to
be achieved by using a minimum number of drivers.
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
FEATURES
Low-power CMOS technology
Fast CPU 8-bit data interface (80xx, 68xx)
Segment output . . . . . . . . . . 61 outputs
Common output . . . . . . . . . . 16 outputs
Duty cycle . . SED1520 . . . 1/16 to 1/32
SED1521 . . . 1/8 to 1/32
Built-in display data RAM. . . 2560 bits
Rich display command setting
On-chip CR oscillation circuit
Recommended expansion segment driver: 80 bit
Master/slave operation is supported
Low power consumption . . . 30µW
LCD voltage . . . . . . . . . . . . . 3.5 to 13V
Single power supply. . . . . . . 2.4 to 7.0V
Package . . . . . . . . . . . . . . . . QFP5-100 pin (FOA, FAA)
QFP15-100 pin (FOC, FAC)
Al pad (DOA, DAA)
Au bump (DOB, DAB)
TAB (TOA)
371-1.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 5
5 Page 
2.0 Block Diagrams
2.3.2 – 2.3.6
2.3.2 Busy Flag
Busy flag being “1” means that the SED1520 is performing its internal operation and any instruction
other than Read Status is disabled. The busy flag is output to pin D7 by a Read Status instruction.
As long as the cycle time (tCYC) requirement is met, the flag need not be checked before each com-
mand and this dramatically improves the MPU performance.
2.3.3 Display Start Line Register
This register is a pointer which determines the start line corresponding to COM0 (normally, the up-
permost line of display) for display of data in the display data RAM. It is used for scrolling the dis-
play or changing the page from one to another. Executing the Set Display Start Line command
sets 5 bits of display start address in this register. Its content is preset in the line counter at each
timing the FR signal changes. The line counter is incremented synchronously to a CL input, thus
generating a line address for sequential reading of 80 bits of data from the display data RAM to the
LCD driver circuit.
2.3.4 Column Address Counter
The column address counter is a 7–bit presettable counter which gives column addresses of the
display data RAM as shown in Fig. 2.3.8.1. When a Read/Write Display Data command comes in,
the counter is incremented by 1. For any nonexisting address over 50H, the counter is locked and
not incremented.
The column address counter is independent from the page register.
2.3.5 Page Register
This register gives a page address of the display data RAM as shown in Fig. 2.3.8.1. The Set Page
Address command permits the MPU to access a new page of the display data RAM.
2.3.6 Display Data RAM
Dot data for display is stored in this RAM. Since the MPU and LCD driver circuit operate indepen-
dently of each other, data can be changed asynchronously without adverse effect on the display.
One bit of the display data RAM is assigned to one bit of LCD:
LCD on = “1”
LCD off = “0”
The ADC command inverts the assignment relationship between a display data RAM column ad-
dress and a segment output (see Fig. 2.3.8.1).
371-1.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SED1521.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| SED1520 | DOT MATRIX LCD DRIVER | ETC |
| SED1520 | LCD Driver Manual |  Epson |
| SED1520D0A | DOT MATRIX LCD DRIVER | ETC |
| SED1521 | DOT MATRIX LCD DRIVER | ETC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |