SERC816 Datasheet PDF - STMicroelectronics
| Part Number | SERC816 | |
| Description | SERCOS INTERFACE CONTROLLER | |
| Manufacturers | STMicroelectronics | |
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SERCON816
SERCOS INTERFACE CONTROLLER
s Single-chip controller for SERCOS interface
s Real time communication for industrial control
systems
s 8/16-bit bus interface, Intel and Motorola control
signals
s Dual port RAM with 2048 word *16-bit
s Data communications via optical fiber rings, RS
485 rings and RS 485 busses
s Maximum transmission rate of 16 Mbaud with
internal clock recovery
s Internal repeater for ring connections
s Full duplex operation
s Modulation of power of optical transmitter diode
s Automatic transmission of synchronous and
data telegrams in the communication cycle
s Flexible RAM configuration, communication
data stored in RAM (single or double buffer) or
transfer via DMA
s Synchronization by external signal
PQFP100
ORDERING NUMBERS: SERC816
SERC816/TR
s Timing control signals
s Automatic service channel transmission
s Watchdog to monitor software and external
synchronization signals
s Compatible mode to SERCON410B SERCOS
interface controller
s 100-pin plastic flat-pack casing
Figure 1. SERCON816 Block Diagram
WRN D[15:0] A[15:0] BUSYN
MCSN0/1
RDN
ALEL
ALEH
BHEN
PCSN0
PCS1
ADMUX
BUSMODE[1:0]
BUSWIDTH
BYTEDIR
SBAUD
SBAUD16
TM0/1
bus interfac e
inter-
rupt
te le g ra m -
proc essing
DMA
c loc k
reset
watc h-
dog
tim ing -
c ontrol
INT0/1
SCLK
SCLKO2/4
MCLK
RSTN
DMAREQR/T
DMAACKNR/T
WDOGN
CYC_CLK
CON_CLK
DIV_CLK
serial interfac e
L_ERRN
RECACTN
IDLE
RxC TxC
RxD TxD[6:1]
optical transm itter/
receiver or
RS-485 bus drive
January 2003
1/23
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SERCON816
2 PIN DESCRIPTION
Table 1. SERCON816 I/O Port Function Summary
Signal(s)
D15-0
ALEL, ALEH
RDN
WRN
BHEN
MCSN0,
MCSN1
PCSN0,
PCS1
BUSYN
DMAREQR
DMAACKRN
DMAREQT
DMAACKTN
ADMUX
BUSMODE0,
BUSMODE1
BUSWIDTH
BYTEDIR
INT0, INT1
SBAUD16
SBAUD
Pin(s)
77-80,
82-85,
87-90,
92-95
54, 53
51
52
75
46,47
48,49
45
38
40
39
41
96
97,98
99
100
44,43
28
29
IO Function
I/O Data bus: for 8-bit-wide bus interfaces, data is written to and read via D7-0, for
16-bit-wide bus interfaces via D15-0. When ADMUX is 1, the address which is
stored in the address latch with ALEL and ALEH is input via D15-0.
I Address latch enable, low and high, active high: they are only used when
ADMUX is 1. When ALEL/ALEH is 1, the signals go from the data bus to the
address bus, when ALEL/ALEH = 0, they store the address. When ADMUX is
0, ALEL/ALEH have to be connected to VDD.
I Read: for the Intel bus interface, data is read when RDN is 0. For the Motorola
bus interface, data is read or written to when RDN is 0 (BUSMODE1 = 0) or
RDN is 1 (BUSMODE1 = 1).
I Write: for the Intel bus interface, data is written to when WRN is 0. For the
Motorola bus interace, WRN selects read (WRN = 1) and write (WRN = 0)
operations of the data bus.
I Byte high enable, active low: in the 16-bit bus mode, data is transferred via
D15-8 when BHEN is 0.
I Memory chip select, active low: to access the internal RAM MCSN0 and
MCSN1 must be 0.
I Periphery chip select, active low (PCSN0) and active high (PCS1): to access
the control registers PCSN0 must equal 0 and PCS1 must equal 1.
O RAM busy, active low: becomes active if an access to an address of the dual
port RAM is performed simultaneously to an access to the same memory
location by the internal telegram processing.
O DMA request receive, active high: becomes active if data from the receive
FIFO can be read. At the beginning of the read operation of the last word of
the receive FIFO, DMAREQR becomes inactive.
I DMA acknowledge receive, active low: when DMAACKRN is 0, the receive
FIFO is read, independent of the levels on A6-1 and the chip select signals.
O DMA request transmit, active high: becomes active when data can be written
to the transmit FIFO. DMAREQT becomes inactive again at the beginning of
the last write access to the transmit FIFO.
I DMA acknowledge transmit, active low: when DMAACKTN is 0, the transmit
FIFO is written to when there is a bus write access independent of the levels
on A6-1 and the chip select signals.
I Address data bus: when ADMUX is 0 A15-0 are the address inputs, when
ADMUX is 1 A15-0 are the outputs of the address latch.
I Bus mode: BUSMODE0 = 0 turns on the Intel bus interface (RDN = read,
WRN = write), BUSMODE0 = 1 selects the Motorola interface (RDN = data
strobe, WRN = read/write). BUSMODE1 selects the 0-active data strobe
(BUSMODE1 = 0) or the 1-active data strobe (BUSMODE1 = 1).
I Bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1).
I Byte address sequence: when BYTEDIR is 0, A0 = 0 addresses the lower 8
bits of a word (low byte first), when BYTEDIR is 1, the upper 8 bits of a word
are addressed (high byte first).
O Interrupts, active low or active high. Interrupt sources and signal polarity are
programmable.
I Baud rate and SERCON410B compatible mode: SBAUD and SBAUD16
selects the baud rate for the serial interface. If SBAUD16 is ‘1’ the
SERCON410B compatible mode is selected.
I Baud rate. Can be overwritten by the microprocessor.
5/23
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| Information | Total 23 Pages | |
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