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74F182 PDF даташит

Спецификация 74F182 изготовлена ​​​​«National» и имеет функцию, называемую «Carry Lookahead Generator».

Детали детали

Номер произв 74F182
Описание Carry Lookahead Generator
Производители National
логотип National логотип 

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74F182 Даташит, Описание, Даташиты
December 1994
54F 74F182
Carry Lookahead Generator
General Description
The ’F182 is a high-speed carry lookahead generator It is
generally used with the ’F181 or ’F381 4-bit arithmetic logic
units to provide high-speed lookahead over word lengths of
more than four bits
Features
Y Provides lookahead carries across a group of four
ALUs
Y Multi-level lookahead high-speed arithmetic operation
over long word lengths
Y Guaranteed 4000V minimum ESD protection
Commercial
74F182PC
74F182SJ (Note 1)
Military
54F182DM (Note 2)
54F182FM (Note 2)
54F182LM (Note 2)
Package
Number
N16E
J16A
M16D
W16A
E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
IEEE IEC
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9492–6
TL F 9492 – 1
TL F 9492 – 2
TL F 9492–3
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9492
RRD-B30M105 Printed in U S A









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74F182 Даташит, Описание, Даташиты
Unit Loading Fan Out
Pin Names
Description
Cn
G0 G2
G1
G3
P0 P1
P2
P3
CnaxbCnaz
G
P
Carry Input
Carry Generate Inputs (Active LOW)
Carry Generate Input (Active LOW)
Carry Generate Input (Active LOW)
Carry Propagate Inputs (Active LOW)
Carry Propagate Input (Active LOW)
Carry Propagate Input (Active LOW)
Carry Outputs
Carry Generate Output (Active LOW)
Carry Propagate Output (Active LOW)
54F 74F
UL
HIGH LOW
10 20
1 0 14 0
1 0 16 0
10 80
10 80
10 60
10 40
50 33 3
50 33 3
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b1 2 mA
20 mA b8 4 mA
20 mA b9 6 mA
20 mA b4 8 mA
20 mA b4 8 mA
20 mA b3 6 mA
20 mA b2 4 mA
b1 mA 20 mA
b1 mA 20 mA
b1 mA 20 mA
Functional Description
The ’F182 carry lookahead generator accepts up to four
pairs of Active LOW Carry Propagate (P0 – P3) and Carry
Generate (G0 – G3) signals and an Active HIGH Carry input
(Cn) and provides anticipated Active HIGH carries (Cn a x
Cnay Cnaz) across four groups of binary adders The
’F182 also has Active LOW Carry Propagate (P) and Carry
Generate (G) outputs which may be used for further levels
of lookahead The logic equations provided at the outputs
are
Cnax
Cnay
Cnaz
e G0 a P0Cn
e G1 a P1G0 a P1P0Cn
e G2 a P2G1 a P2P1G0 a P2P1P0Cn
G e G3 a P3G2 a P3P2G1 a P3P2P1G0
P e P2P2P1P0
Also the ’F182 can be used with binary ALUs in an active
LOW or active HIGH input operand mode The connections
(Figure 1) to and from the ALU to the carry lookahead gen-
erator are identical in both cases Carries are rippled be-
tween lookahead blocks The critical speed path follows the
circled numbers There are several possible arrangements
for the carry interconnects but all achieve about the same
speed A 28-bit ALU is formed by dropping the last ’F181 or
’F381
FIGURE 1 32-Bit ALU with Rippled Carry between 16-Bit Lookahead ALUs
ALUs may be either ’F181 or ’F381
TL F 9492 – 5
2









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74F182 Даташит, Описание, Даташиты
Truth Table
Inputs
Outputs
Cn G0 P0 G1 P1 G2 P2 G3 P3 Cnax Cnay Cnaz G P
X HH
L HX
XLX
HXL
L
L
H
H
X XXHH
X HHHX
L HXHX
XXXLX
X LXXL
HXLXL
L
L
L
H
H
H
X XXXXHH
X XXHHHX
X HHHXHX
L HXHXHX
XXXXXLX
XXXLXXL
X LXXLXL
HXLXLXL
L
L
L
L
H
H
H
H
X XXXXHH
X XXHHHX
X HHHXHX
H HXHXHX
X XXXXLX
X XXLXXL
X LXXLXL
L XLXLXL
H
H
H
H
L
L
L
L
HXXX
XHXX
XXHX
XXXH
LLLL
H
H
H
H
L
Logic Diagram
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
TL F 9492 – 4
3










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