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74F198 PDF даташит

Спецификация 74F198 изготовлена ​​​​«Philips» и имеет функцию, называемую «8-bit bidirectional universal shift register».

Детали детали

Номер произв 74F198
Описание 8-bit bidirectional universal shift register
Производители Philips
логотип Philips логотип 

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74F198 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74F198
8-bit bidirectional universal shift register
Product specification
IC15 Data Handbook
1987 Oct 02
Philips
Semiconductors









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74F198 Даташит, Описание, Даташиты
Philips Semiconductors
8-bit bidirectional universal shift register
Product specification
74F198
FEATURES
Buffered clock and control inputs
Shift right, shift left, and parallel load capability
Asynchronous Master Reset
DESCRIPTION
The 74F198 Bidirectional Universal Shift Register is designed to
incorporate virtually all of the features a system designer may want
in a shift register. This circuit features parallel inputs and outputs,
shift right and shift left serial inputs, operating mode select inputs,
and direct overriding master reset input. The register has four
distinct modes of operation:
– Parallel (broadside) load
– Shift right (in the direction Q0 toward Q7)
– Shift left (in the direction Q7 toward Q0)
– Inhibit clock (do nothing).
Synchronous parallel loading is accomplished by applying the 8 bits
of data and taking both mode control inputs, S0 and S1, High. The
data is loaded into the associated flip-flop and appears at the
outputs after the positive transition of the clock inputs. During
loading, serial data flow is inhibited.
Shift right is accomplished synchronously, with the rising edge of the
clock pulse when S0 is High and S1 is Low. Serial data for this
mode is entered at the right data input (DSR). When S0 is Low and
S1 is High, data shifts left synchronously and new data is entered at
the shift-left serial input (DSL).
Clocking of the flip-flops is inhibited when both mode control inputs
are Low.
PIN CONFIGURATION
S0 1
DSR 2
D0 3
Q0 4
D1 5
Q1 6
D2 7
Q2 8
D3 9
Q3 10
CP 11
GND 12
24 VCC
23 S1
22 DSL
21 D7
20 Q7
19 D6
18 Q6
17 D5
16 Q5
15 D4
14 Q4
13 MR
SF00160
TYPE
74F198
TYPICAL fMAX
95MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
73mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
24-pin Plastic Slim
DIP (300mil)
N74F198N
24-pin Plastic SOL
N74F198D
PKG DWG #
SOT222-1
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
D0–D7
Parallel data inputs
1.0/1.0
DSR
DSL
S0–S1
Serial data input (Shift Right)
Serial data input (Shift Left)
Mode Select inputs
1.0/1.0
1.0/1.0
1.0/1.0
CP Clock Pulse input (Active rising edge)
1.0/1.0
MR Master Reset input (Active Low)
1.0/1.0
Q0–Q7
Data outputs
50/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
October 2, 1987
2 853–0089 90746









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74F198 Даташит, Описание, Даташиты
Philips Semiconductors
8-bit bidirectional universal shift register
Product specification
74F198
LOGIC SYMBOL
2 3 5 7 9 15 17 19 21 22
DSR D0 D1 D2 D3 D4 D5 D6 D7 DSL
13 MR
1 S0
23 S1
11 CP
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC = Pin 24
GND = Pin 12
4 6 8 10 14 16 18 20
SF00161
IEC/IEEE SYMBOL
SRG8
13 R
1
23
0 M0
13
11 C4
1 /2
2 1, 4D
3 3, 4D
5 3, 4D
7
9
15
17
19
21 3, 4D
22 2, 4D
4
6
8
10
14
16
18
20
SF00162
FUNCTION TABLE
INPUTS
OUTPUTS
MODE
SERIAL
MR CP
S0 S1
LEFT
RIGHT
PARALLEL
07
Q0 Q1 Q6 Q7
LXXX
X
X
X LL
LL
HXX L
X
X
X Q00 Q10
Q60 Q70
HHH
X
X
07
01
67
HHL
X
H
X H Q0n
Q5n Q6n
HHL
X
L
X L Q0n
Q5n Q6n
HLH
H
X
X Q1n Q2n
Q7n H
HLH
L
X
X Q1n Q2n
Q7n L
HL LX
X
X
X Q00 Q10
Q60 Q70
H = High voltage level
L = Low voltage level
X = Don’t care
= Low-to-High transition of designated input
07 = The level of steady input at inputs 0 through 7, respectively.
Q00, Q10, Q60, Q70 = The level of Q0, Q1, Q6, Q7, respectively, before the indicated steady state input conditions were established.
Q0n, Q1n, Q6n, Q7n = The level of Q0, Q1, Q6, Q7, respectively, before the most recent Low-to-High clock transition.
October 2, 1987
3










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