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74F225 PDF даташит

Спецификация 74F225 изготовлена ​​​​«Philips» и имеет функцию, называемую «16X5 asynchronous FIFO 3-State».

Детали детали

Номер произв 74F225
Описание 16X5 asynchronous FIFO 3-State
Производители Philips
логотип Philips логотип 

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74F225 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74F225
16X5 asynchronous FIFO (3-State)
Product specification
IC15 Data Handbook
1992 Jun 15
Philips
Semiconductors









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74F225 Даташит, Описание, Даташиты
Philips Semiconductors
16 × 5 asynchronous FIFO (3-State)
Product specification
74F225
FEATURES
Independent synchronous inputs and outputs
Organized as 16 words of 5 bits
DC to 25MHz data rate
3–State outputs
Cascadable in word–width and depth direction
DESCRIPTION
This 80–bit active element First–In–First–Out (FIFO) is a monolithic
Schottky–clamped transistor–transistor logic (STTL) array organized
as 16–words of 5–bits each. A memory system using the ’F225 can
be easily expanded in multiples of 16–words of 5–bits as shown in
Figure 1. The 3–State outputs controlled by a single enable input
(OE) make bus connection and multiplexing simple. The ’F225
processes data in a parallel format at any desired clock rate from
DC to 25MHz. Status of the ’F225 is provided by three outputs, Input
Ready (IR), Unload Clock Output (UNCPOUT) and Output Ready
(OR). The data outputs are non–inverting with respect to the data
inputs and are disabled when the OE input is High. When OE is
Low, the data outputs are enabled to function as totem–pole outputs.
TYPE
74F225
TYPICAL fMAX
25MHz
TYPICAL SUPPLY
CURRENT
( TOTAL)
65mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
20–pin plastic DIP
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
N74F225N
20–pin plastic SOL
N74F225D
PKG DWG #
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
CPA, CPB
Load clock A and load clock B inputs
1.0/0.033
D0 – D4
Data inputs
1.0/0.033
OE Output enable input (active–Low)
1.0/0.033
UNCPIN
Unload clock input
1.0/0.033
MR Master reset input (active–Low)
1.0/0.033
IR Input ready output
50/33
UNCPOUT
Unload clock output (active–Low)
50/33
Q0 – Q4
Data outputs
150/40
OR Output ready output
50/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
1.0mA/20mA
3.0mA/24mA
1.0mA/20mA
RESET MODE
A High–to–Low transition on the Master Reset (MR) input invalidates
all data stored in the FIFO by clearing the control logic and setting
OR Low. This High–to–Low transition on the MR input does not
effect the data outputs but since OR is driven Low, it signifies invalid
data on the outputs.
WRITE MODE
Data may be written into the array on the Low–to–High transition of
either load clock (CPA or CPB) input. When writing data into the
FIFO, one of the load clock inputs must be held High while the other
strobes data into the FIFO. This arrangement allows either load
clock to function as an inhibit for the other. Input Ready (IR)
monitors the status of the last word location and signifies when the
FIFO is full. This output is High whenever the FIFO is available to
accept new data. The unload clock output (UNCPOUT) also
monitors the last word location. This output generates a
Low–logic–level pulse (synchronized to the internal clock pulse)
when the last word location is vacant
READ MODE
The Output Ready (OR) output is High when valid data is present on
the data outputs. Data in the array is shifted on the Low–to–High
transition of the Unload Clock Input (UNCPIN). In order for Output
Ready (OR) to go High, Unload Clock Input (UNCPIN) must also be
High.
June 15, 1992
2 853-1652 06992









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74F225 Даташит, Описание, Даташиты
Philips Semiconductors
16 × 5 asynchronous FIFO (3-State)
Product specification
74F225
PIN CONFIGURATION
CPA 1
IR 2
UNCPOUT 3
D0 4
D1 5
D2 6
D3 7
D4 8
OE 9
GND 10
LOGIC SYMBOL
20 VCC
19 CPB
18 MR
17 OR
16 UNCPIN
15 Q0
14 Q1
13 Q2
12 Q3
11 Q4
SF00334
4 5 67 8
D0 D1 D2 D3 D4
1 CPA
19 CPB
16 UNCPIN
UNCPOUT 3
9 OE
18 MR
Q0 Q1 Q2 Q3 Q4 IR OR
VCC = Pin 20
GND = Pin 10
15 14 13 12 11 2 17
SF00335
IEC/IEEE SYMBOL
FIFO 16 X
9 EN5 5 CTR
18 CT=0
3
CT<16 &
+
1 1 G1
19 G2/Z3
CT>0 &
2CT<16
16 Z4 4
3
2
17
4
1D
5
5 15
14
6 13
7 12
8 11
SF00336
June 15, 1992
3










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