74F273SC PDF даташит
Спецификация 74F273SC изготовлена «Fairchild» и имеет функцию, называемую «Octal D-Type Flip-Flop». |
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Детали детали
Номер произв | 74F273SC |
Описание | Octal D-Type Flip-Flop |
Производители | Fairchild |
логотип |
6 Pages
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April 1988
Revised August 1999
74F273
Octal D-Type Flip-Flop
General Description
The 74F273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s Ideal buffer for MOS microprocessor or memory
s Eight edge-triggered D-type flip-flops
s Buffered common clock
s Buffered, asynchronous Master Reset
s See 74F377 for clock enable version
s See 74F373 for transparent latch version
s See 74F374 for 3-STATE version
Ordering Code:
Order Number Package Number
Package Description
74F273SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F273PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009511
www.fairchildsemi.com
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Unit Loading/Fan Out
Pin Names
D0–D7
MR
CP
Q0–Q7
Description
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
Mode Select-Function Table
Operating Mode
Reset (Clear)
Load “1”
Load “0”
Inputs
Output
MR CP Dn Qn
LXXL
H h H
H l
L
H = HIGH Voltage Level steady state
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L = LOW Voltage Level steady state
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition
X = Immaterial
= LOW-to-HIGH clock transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
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Absolute Maximum Ratings(Note 1)
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Junction Temperature under Bias
−55°C to +150°C
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
3-STATE Output
−0.5V to VCC
−0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
ESD Last Passing Voltage (min)
4000V
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VCC
Conditions
VIH
VIL
VCD
VOH
VOL
IIH
IBVI
ICEX
VID
IOD
IIL
IOS
ICCH
ICCL
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
10% VCC
5% VCC
10% VCC
5% VCC
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
2.0
2.5
2.7
4.75
−60
V Recognized as a HIGH Signal
0.8 V
Recognized as a LOW Signal
−1.2 V Min IIN = −18 mA
V Min IOH = −1 mA
0.5
0.5 V Min IOL = 20 mA
5.0 µA Max VIN = 2.7V
7.0 µA Max VIN = 7.0V
50 µA Max VOUT = VCC
V 0.0 IID = 1.9 µA
All other pins grounded
3.75
µA
0.0 VIOD = 150 mV
All other pins grounded
−0.6 mA Max VIN = 0.5V
−150 mA Max VOUT = 0V
44 CP =
mA Max
56 Dn = MR = HIGH
3 www.fairchildsemi.com
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Номер в каталоге | Описание | Производители |
74F273SC | Octal D-Type Flip-Flop | Fairchild |
74F273SC | Octal D Flip-Flop | National |
74F273SJ | Octal D-Type Flip-Flop | Fairchild |
74F273SJ | Octal D Flip-Flop | National |
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