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74F377SJ PDF даташит

Спецификация 74F377SJ изготовлена ​​​​«National» и имеет функцию, называемую «Octal D Flip-Flop with Clock Enable».

Детали детали

Номер произв 74F377SJ
Описание Octal D Flip-Flop with Clock Enable
Производители National
логотип National логотип 

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74F377SJ Даташит, Описание, Даташиты
May 1995
54F 74F377
Octal D Flip-Flop with Clock Enable
General Description
The ’F377 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs The common buffered
Clock (CP) input loads all flip-flops simultaneously when the
Clock Enable (CE) is LOW
The register is fully edge-triggered The state of each D in-
put one setup time before the LOW-to-HIGH clock tran-
sition is transferred to the corresponding flip-flop’s Q out-
put The CE input must be stable only one setup time prior
to the LOW-to-HIGH clock transition for predictable opera-
tion
Features
Y Ideal for addressable register applications
Y Clock enable for address and data synchronization
applications
Y Eight edge-triggered D flip-flops
Y Buffered common clock
Y See ’F273 for master reset version
Y See ’F373 for transparent latch version
Y See ’F374 for TRI-STATE version
Y Guaranteed 4000V minimum ESD protection
Commercial
74F377PC
74F377SC (Note 1)
74F377SJ (Note 1)
Military
54F377DM (QB)
54F377FM (QB)
54F377LM (QB)
Package
Number
N20A
J20A
M20B
M20D
W20A
E20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Logic Symbols
IEEE IEC
TL F 9525 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9525
TL F 9525 – 4
RRD-B30M75 Printed in U S A









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74F377SJ Даташит, Описание, Даташиты
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
Unit Loading Fan Out
Pin Names
Description
D0 – D7
CE
CP
Q0 – Q7
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
TL F 9525–2
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
Operating Mode
Load ‘‘1’’
Load ‘‘0’’
Hold
(Do Nothing)
Mode Select-Function Table
Inputs
CP CE
LI
LI
Lh
XH
Dn
h
I
X
X
Output
Qn
H
L
No Change
No Change
TL F 9525 – 3
H e HIGH Voltage Level
h e HIGH Voltage Level one setup time prior to
the LOW-to-HIGH Clock Transition
L e LOW Voltage Level
I e LOW Voltage Level one setup time prior to
the LOW-to-HIGH Clock Transition
X e Immaterial
L e LOW-to-HIGH Clock Transition
Logic Diagram
TL F 9525 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2









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74F377SJ Даташит, Описание, Даташиты
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b65 C to a150 C
Ambient Temperature under Bias
b55 C to a125 C
Junction Temperature under Bias
Plastic
b55 C to a175 C
b55 C to a150 C
VCC Pin Potential to
Ground Pin
b0 5V to a7 0V
Input Voltage (Note 2)
b0 5V to a7 0V
Input Current (Note 2)
b30 mA to a5 0 mA
Voltage Applied to Output
in HIGH State (with VCC e 0V)
Standard Output
TRI-STATE Output
b0 5V to VCC
b0 5V to a5 5V
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated IOL (mA)
4000V
Note 1 Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2 Either voltage limit or current limit is sufficient to protect inputs
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
b55 C to a125 C
0 C to a70 C
Supply Voltage
Military
Commercial
a4 5V to a5 5V
a4 5V to a5 5V
DC Electrical Characteristics
Symbol
VIH
VIL
VCD
VOH
VOL
IIH
IBVI
IIL
IOS
ICEX
VID
IOD
ICCH
ICCL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
54F 10% VCC
74F 10% VCC
74F 5% VCC
Output LOW
Voltage
54F 10% VCC
74F 10% VCC
Input HIGH Current
Input HIGH Current
Breakdown Test
Input LOW Current
Output Short-Circuit Current
Output HIGH Leakage Current
Input Leakage Test
Output Leakage Circuit Current
Power Supply Current
54F 74F
Min Typ Max
20
08
b1 2
25
25
27
05
05
50
70
b60
b0 6
b150
50
4 75
3 75
35 46
44 56
Units
V
V
V
V
V
mA
mA
mA
mA
mA
V
mA
mA
VCC
Min
Min
Min
Max
Max
Max
Max
Max
00
00
Max
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
IIN e b18 mA
IOH e b1 mA
IOH e b1 mA
IOH e b1 mA
IOL e 20 mA
IOL e 20 mA
VIN e 2 7V
VIN e 7 0V
VIN e 0 5V
VOUT e 0V
VOUT e VCC
IID e 1 9 mA
All Other Pins Grounded
VIOD e 150 mV
All Other Pins Grounded
CP e L
Dn e MR e HIGH
3










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74F377SCOctal D Flip-Flop with Clock EnableNational
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74F377SJOctal D-Type Flip-Flop with Clock EnableFairchild
Fairchild
74F377SJOctal D Flip-Flop with Clock EnableNational
National

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