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Спецификация 74F382SJ изготовлена «Fairchild» и имеет функцию, называемую «4-Bit Arithmetic Logic Unit». |
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Детали детали
Номер произв | 74F382SJ |
Описание | 4-Bit Arithmetic Logic Unit |
Производители | Fairchild |
логотип |
8 Pages
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May 1988
Revised August 1999
74F382
4-Bit Arithmetic Logic Unit
General Description
The 74F382 performs three arithmetic and three logic oper-
ations on two 4-bit words, A and B. Two additional Select
input codes force the Function outputs LOW or HIGH. An
Overflow output is provided for convenience in twos com-
plement arithmetic. A Carry output is provided for ripple
expansion. For high-speed expansion using a Carry Looka-
head Generator, refer to the 74F381 data sheet.
Features
s Performs six arithmetic and logic functions
s Selectable LOW (clear) and HIGH (preset) functions
s LOW input loading minimizes drive requirements
s Carry output for ripple expansion
s Overflow output for twos complement arithmetic
Ordering Code:
Order Number Package Number
Package Description
74F382SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F382SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F382PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009529
www.fairchildsemi.com
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Unit Loading/Fan Out
Pin Names
A0–A3
B0–B3
S0–S2
Cn
Cn + 4
OVR
F0–F3
Description
A Operand Inputs
B Operand Inputs
Function Select Inputs
Carry Input
Carry Output
Overflow Output
Function Outputs
U.L.
HIGH/LOW
1.0/4.0
1.0/4.0
1.0/1.0
1.0/5.0
50/33.3
50/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−2.4 mA
20 µA/−2.4 mA
20 µA/−0.6 mA
20 µA/−3.0 mA
−1 mA/20 mA
−1 mA/20 mA
−1 mA/20 mA
Functional Description
Signals applied to the Select inputs S0–S2 determine the
mode of operation, as indicated in the Function Select
Table. An extensive listing of input and output levels is
shown in the Truth Table. The circuit performs the arith-
metic functions for either active HIGH or active LOW oper-
ands, with output levels in the same convention. In the
Subtract operating modes, it is necessary to force a carry
(HIGH for active HIGH operands, LOW for active LOW
operands) into the Cn input of the least significant package.
Ripple expansion is illustrated in Figure 2. The overflow
output OVR is the Exclusive-OR of Cn + 3 and Cn + 4; a
HIGH signal on OVR indicates overflow in twos comple-
ment operation. Typical delays for Figure 2 are given in
Figure 1.
Function Select Table
Select
S0 S1
LL
HL
LH
HH
LL
HL
LH
HH
H = HIGH Voltage Level
L = LOW Voltage Level
Operation
S2
L Clear
L B Minus A
L A Minus B
L A Plus B
H A⊕B
H A+B
H AB
H Preset
Path Segment
Toward
F
A1 or B1 to Cn + 4
Cn to Cn + 4
Cn to Cn + 4
Cn to F
Cn to Cn + 4, OVR
Total Delay
6.5 ns
6.3 ns
6.3 ns
8.1 ns
—
27.2 ns
FIGURE 1. 16-Bit Delay Tabulation
Output
Cn + 4, OVR
6.5 ns
6.3 ns
6.3 ns
—
8.0 ns
27.1 ns
FIGURE 2. 16-Bit Ripply Carry ALU Expansion
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Truth Table
Inputs
Outputs
Function
S0
S1
S2 Cn An Bn
F0
F1
F2
F3 OVR
Cn + 4
CLEAR
L L L LXXL L L L H
H
HXXL L L L H
H
B MINUS A H L L L L L H H H H L
L
L LHLHHH L
H
LHL L L L L
L
L
L HHHHHH
L
L
HL L L L L L
L
H
H LHHHHH
L
H
HHLHL L L
L
L
HHHL L L L
L
H
A MINUS B L H L L L L H H H H L
L
L LHL L L L
L
L
LHL
L HHH
L
H
L HHHHHH
L
L
HL L L L L L
L
H
H LHH L L L
L
L
HH LHHHH
L
H
HHHL L L L
L
H
A PLUS B
HHL L L L L L L L
L
L
L LHHHHH L
L
LH LHHHH
L
L
L HH L HHH
L
H
HL LHL LL
L
L
HLHL L L L
L
H
HHL L L L L
L
H
HHHHHHH
L
H
A⊕B
L LHXL L L L L L
L
L
X LHHHHH
L
L
LH LHHHH
L
L
XHHL L L L H
H
HH LHHHH H
H
A+B
HLHXL L L L L L
L
L
X LHHHHH
L
L
XH LHHHH
L
L
L HHHHHH
L
L
HHHHHHH
H
H
AB
LHHX L L L L L L H
H
XLHL L L L
L
L
XHL L L L L H
H
L HHHHHH
L
L
HHHHHHH
H
H
PRESET
HHHX L
L HHHH
L
L
X LHHHHH
L
L
XH LHHHH
L
L
L HHHHHH
L
L
HHHHHHH
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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