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74F403ASPC PDF даташит

Спецификация 74F403ASPC изготовлена ​​​​«Fairchild» и имеет функцию, называемую «First-In First-Out (FIFO) Buffer Memory».

Детали детали

Номер произв 74F403ASPC
Описание First-In First-Out (FIFO) Buffer Memory
Производители Fairchild
логотип Fairchild логотип 

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74F403ASPC Даташит, Описание, Даташиты
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January 1989
Revised May 1999
74F403A
First-In First-Out (FIFO) Buffer Memory
General Description
The 74F403A is an expandable fall-through type high-
speed First-In First-Out (FIFO) Buffer Memory optimized
for high-speed disk or tape controllers and communication
buffer applications. It is organized as 16-words by 4-bits
and may be expanded to any number of words or any num-
ber of bits in multiples of four. Data may be entered or
extracted asynchronously in serial or parallel, allowing eco-
nomical implementation of buffer memories.
The 74F403A has 3-STATE outputs which provide added
versatility and is fully compatible with all TTL families.
Features
s Serial or parallel input
s Serial or parallel output
s Expandable without external logic
s 3-STATE outputs
s Fully compatible with all TTL families
s Slim 24-pin package
s 9403A replacement
s Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number Package Number
Package Description
74F403ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
© 1999 Fairchild Semiconductor Corporation DS009536.prf
www.fairchildsemi.com









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74F403ASPC Даташит, Описание, Даташиты
Unit Loading/Fan Out:
See Section 2 for U.L. definitions
Pin
Names
Description
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
D0 D3 Parallel Data Inputs
DS Serial Data Input
PL Parallel Load Input
CPSI Serial Input Clock
IES Serial Input Enable
TTS Transfer to Stack Input
OES Serial Output Enable
TOS Transfer Out Serial
TOP Transfer Out Parallel
MR Master Reset
OE Output Enable
CPSO Serial Output Clock
Q0 Q3 Parallel Data Outputs
QS Serial Data Output
IRF Input Register Full
ORE Output Register Empty
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
1.0/0.667
285/26.7
285/26.7
20/13.3
20/13.3
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
5.7 mA/16 mA
5.7 mA/16 mA
400 µA/8 mA
400 µA/8 mA
Block Diagram
Functional Description
As shown in the Block Diagram the 74F403A consists of
three sections:
1. An Input register with parallel and serial data inputs as
well as control inputs and outputs for input handshak-
ing and expansion.
2. A 4-bit wide, 14-word deep fall-through stack with self-
contained control logic.
3. An Output Register with parallel and serial data outputs
as well as control inputs and outputs for output hand-
shaking and expansion.
Since these three sections operate asynchronously and
almost independently, they will be described separately
below.
INPUT REGISTER (DATA ENTRY)
The Input Register can receive data in either bit-serial or in
4-bit parallel form. It stores this data until it is sent to the
fall-through stack and generates the necessary status and
control signals.
Figure 1 is a conceptual logic diagram of the input section.
As described later, this 5-bit register is initialized by setting
the F3 flip-flop and resetting the other flip-flops. The Q out-
put of the last flip-flop (FC) is brought out as the “Input
Register Full” output (IRF). After initialization this output is
HIGH.
Parallel Entry— A HIGH on the PL input loads the D0-D3
inputs into the F0-F3 flip-flops and sets the FC flip-flop. This
forces the IRF output LOW indicating that the input register
is full. During parallel entry, the CPSI input must be LOW. If
parallel expansion is not being implemented, IES must be
LOW to establish row mastership (see Expansion section).
Serial Entry— Data on the DS input is serially entered into
the F3, F2, F1, F0, FC shift register on each HIGH-to-LOW
transition of the CPSI clock input, provided IES and PL are
LOW.
After the fourth clock transition, the four data bits are
located in the four flip-flops, F0-F3. The FC flip-flop is set,
forcing the IRF output LOW and internally inhibiting CPSI
clock pulses from affecting the register, Figure 2 illustrates
the final positions in a 74F403A resulting from a 64-bit
serial bit train. B0 is the first bit, B63 the last bit.
www.fairchildsemi.com
2









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74F403ASPC Даташит, Описание, Даташиты
FIGURE 1. Conceptual Input Section
FIGURE 2. Final Positions in a 74F403A
Resulting from a 64-Bit Serial Train
Transfer to the Stack— The outputs of Flip-Flops F0-F3
feed the stack. A LOW level on the TTS input initiates a
“fall-through” action. If the top location of the stack is
empty, data is loaded into the stack and the input register is
re-initialized. Note that this initialization is postponed until
PL is LOW again. Thus, automatic FIFO action is achieved
by connecting the IRF output to the TTS input.
An RS Flip-Flop (the Request Initialization Flip-Flop shown
in Figure 10) in the control section records the fact that
data has been transferred to the stack. This prevents multi-
ple entry of the same word into the stack despite the fact
the IRF and TTS may still be LOW. The Request Initializa-
tion Flip-Flop is not cleared until PL goes LOW. Once in the
stack, data falls through the stack automatically, pausing
only when it is necessary to wait for an empty next location.
In the 74F403A as in most modern FIFO designs, the MR
input only initializes the stack control section and does not
clear the data.
OUTPUT REGISTER (DATA EXTRACTION)
The Output Register receives 4-bit data words from the
bottom stack location, stores it and outputs data on a 3-
STATE 4-bit parallel data bus or on a 3-STATE serial data
bus. The output section generates and receives the neces-
sary status and control signals. Figure 3 is a conceptual
logic diagram of the output section.
3 www.fairchildsemi.com










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