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74F433SPC PDF даташит

Спецификация 74F433SPC изготовлена ​​​​«Fairchild» и имеет функцию, называемую «First-In First-Out (FIFO) Buffer Memory».

Детали детали

Номер произв 74F433SPC
Описание First-In First-Out (FIFO) Buffer Memory
Производители Fairchild
логотип Fairchild логотип 

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74F433SPC Даташит, Описание, Даташиты
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April 1988
Revised August 1999
74F433
First-In First-Out (FIFO) Buffer Memory
General Description
The 74F433 is an expandable fall-through type high-speed
First-In First-Out (FIFO) Buffer Memory that is optimized for
high-speed disk or tape controller and communication
buffer applications. It is organized as 64-words by 4-bits
and may be expanded to any number of words or any num-
ber of bits in multiples of four. Data may be entered or
extracted asynchronously in serial or parallel, allowing eco-
nomical implementation of buffer memories.
The 74F433 has 3-STATE outputs that provide added ver-
satility, and is fully compatible with all TTL families.
Features
s Serial or parallel input
s Serial or parallel output
s Expandable without additional logic
s 3-STATE outputs
s Fully compatible with all TTL families
s Slim 24-pin package
s 9423 replacement
Ordering Code:
Order Number Package Number
Package Description
74F433SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Logic Symbol
Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS009544
www.fairchildsemi.com









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74F433SPC Даташит, Описание, Даташиты
Unit Loading/Fan Out
Pin Names
Description
PL
CPSI
IES
TTS
MR
OES
TOP
TOS
CPSO
OE
D0–D3
DS
Q0–Q3
QS
IRF
ORE
Block Diagram
Parallel Load Input
Serial Input Clock
Serial Input Enable
Transfer to Stack Input
Master Reset
Serial Output Enable
Transfer Out Parallel
Transfer Out Serial
Serial Output Clock
Output Enable
Parallel Data Inputs
Serial Data Input
Parallel Data Outputs
Serial Data Output
Input Register Full
Output Register Empty
U.L.
HIGH/LOW
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
1.0/0.66
285/10
285/10
20/5
20/5
Input IIH/IIL
Output IOH/IOL
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
20 µA/400 µA
5.7 mA/16 mA
5.7 µA/16 mA
400 µA/8 mA
400 µA/8 mA
www.fairchildsemi.com
2









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74F433SPC Даташит, Описание, Даташиты
Functional Description
As shown in the block diagram, the 74F433 consists of
three sections:
1. An Input Register with parallel and serial data inputs,
as well as control inputs and outputs for input hand-
shaking and expansion.
2. A 4-bit-wide, 62-word-deep fall-through stack with self-
contained control logic.
3. An Output Register with parallel and serial data out-
puts, as well as control inputs and outputs for output
handshaking and expansion.
These three sections operate asynchronously and are vir-
tually independent of one another.
Input Register (Data Entry)
The Input Register can receive data in either bit-serial or 4-
bit parallel form. It stores this data until it is sent to the fall-
through stack, and also generates the necessary status
and control signals.
This 5-bit register (see Figure 1) is initialized by setting flip-
flop F3 and resetting the other flip-flops. The Q-output of
the last flip-flop (FC) is brought out as the Input Register
Full (IRF) signal. After initialization, this output is HIGH.
Parallel Entry—A HIGH on the Parallel Load (PL) input
loads the D0–D3 inputs into the F0–F3 flip-flops and sets
the FC flip-flop. This forces the IRF output LOW, indicating
that the input register is full. During parallel entry, the Serial
Input Clock (CPSI) input must be LOW.
Serial Entry—Data on the Serial Data (DS) input is serially
entered into the shift register (F3, F2, F1, F0, FC) on each
HIGH-to-LOW transition of the CPSI input when the Serial
Input Enable (IES) signal is LOW. During serial entry, the
PL input should be LOW.
After the fourth clock transition, the four data bits are
located in flip-flops F0–F3. The FC flip-flop is set, forcing
the IRF output LOW and internally inhibiting CPSI pulses
from affecting the register. Figure 2 illustrates the final posi-
tions in an 74F433 resulting from a 256-bit serial bit train
(B0 is the first bit, B255 the last).
FIGURE 1. Conceptual Input Section
3 www.fairchildsemi.com










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Номер в каталогеОписаниеПроизводители
74F433SPCFirst-In First-Out (FIFO) Buffer MemoryFairchild
Fairchild

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