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74F524SC PDF даташит

Спецификация 74F524SC изготовлена ​​​​«Fairchild» и имеет функцию, называемую «8-Bit Registered Comparator».

Детали детали

Номер произв 74F524SC
Описание 8-Bit Registered Comparator
Производители Fairchild
логотип Fairchild логотип 

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74F524SC Даташит, Описание, Даташиты
April 1988
Revised August 1999
74F524
8-Bit Registered Comparator
General Description
The 74F524 is an 8-bit bidirectional register with parallel
input and output plus serial input and output progressing
from LSB to MSB. All data inputs, serial and parallel, are
loaded by the rising edge of the input clock. The device
functions are controlled by two control lines (S0, S1) to exe-
cute shift, load, hold and read out.
An 8-bit comparator examines the data stored in the regis-
ters and on the data bus. Three true-HIGH, open-collector
outputs representing “register equal to bus”, “register
greater than bus” and “register less than bus” are provided.
These outputs can be disabled to the OFF state by the use
of Status Enable (SE). A mode control has also been pro-
vided to allow twos complement as well as magnitude com-
pare. Linking inputs are provided for expansion to longer
words.
Features
s 8-Bit bidirectional register with bus-oriented input-output
s Independent serial input-output to register
s Register bus comparator with “equal to”, “greater than”
and “less than” outputs
s Cascadable in groups of eight bits
s Open-collector comparator outputs for AND-wired
expansion
s Twos complement or magnitude compare
Ordering Code:
Order Number Package Number
Package Description
74F524SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F524PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009546
www.fairchildsemi.com









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74F524SC Даташит, Описание, Даташиты
Unit Loading/Fan Out
Pin Names
Description
U.L.
HIGH/LOW
Input IIH/IIL
Output IOH/IOL
S0, S1
C/SI
Mode Select Inputs
Status Priority or Serial Data Input
1.0/1.0
1.0/1.0
20 µA/0.6 mA
20 µA/0.6 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20 µA/0.6 mA
SE Status Enable Input (Active LOW)
1.0/1.0
20 µA/0.6 mA
M Compare Mode Select Input
1.0/1.0
20 µA/0.6 mA
I/O0–I/O7 Parallel Data Inputs or
3-STATE Parallel Data Outputs
3.5/1.083
150/40 (33.3)
70 µA/0.65 mA
3 mA/24 mA (20 mA)
C/SO
Status Priority or Serial Data Output
50/33.3
1 mA/20 mA
LT
Register Less Than Bus Output
OC (Note 1) /33.3 (Note 1) /20 mA
EQ Register Equal Bus Output
OC(Note 1) /33.3 (Note 1) /20 mA
GT
Note 1: OC = Open Collector
Register Greater Than Bus Output
OC(Note 1) /33.3 (Note 1) /20 mA
Number Representation Select Table
M Operation
L Magnitude Compare
H Twos Complement Compare
Select Truth Table
S0 S1
Operation
L L Hold—Retains Data in Shift Register
L H Read—Read Contents in Register onto Data Bus,
Data Remains in Register Unaffected by Clock
H L Shift—Allows Serial Shifting on Next Rising Clock Edge
H H Load—Load Data on Bus into Register
Status Truth Table
(Hold Mode)
SE C/SI
HH
LL
XL
HL
HH
HH
LH
1 = HIGH if data are equal, otherwise LOW
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Inputs
Data Comparison
X
OA–OH > I/O0–I/O7
OA–OH = I/O0–I/O7
OA–OH < I/O0–I/O7
OA–OH > I/O0–I/O7
OA–OH = I/O0–I/O7
OA–OH < I/O0–I/O7
Outputs
EQ GT
LT
HHH
L HH
HHH
L HH
LHL
HL L
L LH
C/SO
1
L
L
L
L
H
L
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74F524SC Даташит, Описание, Даташиты
Functional Description
The 74F524 contains eight D-type flip-flops connected as a
shift register with provision for either parallel or serial load-
ing. Parallel data may be read from or loaded into the regis-
ters via the data bus I/O0–I/O7. Serial data is entered from
the C/SI input and may be shifted into the register and out
through the C/SO output. Both parallel and serial data entry
occur on the rising edge of the input clock (CP). The opera-
tion of the shift register is controlled by two signals S0 and
S1 according to the Select Truth Table. The 3-STATE paral-
lel output buffers are enabled only in the Read mode.
One port of an 8-bit comparator is attached to the data bus
while the other port is tied to the outputs of the internal reg-
ister. Three active-OFF, open-collector outputs indicate
whether the contents held in the shift register are “greater
than”, (GT), “less than” (LT), or “equal to” (EQ) the data on
the input bus. A HIGH signal on the Status Enable (SE)
input disables these outputs to the OFF state. A mode con-
trol input (M) allows selection between a straightforward
magnitude compare or a comparison between twos com-
plement numbers.
For “greater than” or “less than” detection, the C/SI input
must be held HIGH, as indicated in the Status Truth Table.
The internal logic is arranged such that a LOW signal on
the C/SI input disables the “greater than” and “less than”
outputs. The C/SO output will be forced HIGH if the “equal
to” status condition exists, otherwise C/SO will be held
LOW. These facilities enable the 74F524 to be cascaded
for word length greater than eight bits.
Word length expansion (in groups of eight bits) can be
achieved by connecting the C/SO output of the more signif-
Function Diagram
icant byte to the C/SI input of the next less significant byte
and also to its own SE input (see Figure 1). The C/SI input
of the most significant device is held HIGH while the SE
input of the least significant device is held LOW. The corre-
sponding status outputs are AND-wired together. In the
case of twos complement number compare, only the Mode
input to the most significant device should be HIGH. The
Mode inputs to all other cascaded devices are held LOW.
Suppose that an inequality condition is detected in the
most significant device. Assuming that the byte stored in
the register is greater than the byte on the data bus, the EQ
and LT outputs will be pulled LOW and the GT output will
float HIGH. Also the C/SO output of the most significant
device will be forced LOW, disabling the subsequent
devices but enabling its own status outputs. The correct
status condition is thus indicated. The same applies if the
registered byte is less than the data byte, only in this case
the EQ and GT outputs go LOW and LT output floats HIGH.
If an equality condition is detected in the most significant
device, its C/SO output is forced HIGH. This enables the
next less significant device and also disables its own status
outputs. In this way, the status output priority is handed
down to the next less significant device which now effec-
tively becomes the most significant byte. The worst case
propagation delay for a compare operation involving “n”
cascaded 74F524s will be when an equality condition is
detected in all but the least significant byte. In this case, the
status priority has to ripple all the way down the chain
before the correct status output is established. Typically,
this will take 35 + 6(n2) ns.
FIGURE 1. Cascading 74F524s for Comparing Longer Words
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Номер в каталогеОписаниеПроизводители
74F524SC8-Bit Registered ComparatorFairchild
Fairchild

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