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74F533 PDF даташит

Спецификация 74F533 изготовлена ​​​​«Fairchild» и имеет функцию, называемую «Octal Transparent Latch with 3-STATE Outputs».

Детали детали

Номер произв 74F533
Описание Octal Transparent Latch with 3-STATE Outputs
Производители Fairchild
логотип Fairchild логотип 

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74F533 Даташит, Описание, Даташиты
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April 1988
Revised October 2000
74F533
Octal Transparent Latch with 3-STATE Outputs
General Description
The 74F533 consists of eight latches with 3-STATE outputs
for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state. The 74F533 is the same as the
74F373, except that the outputs are inverted.
Features
s Eight latches in a single package
s 3-STATE outputs for bus interfacing
s Inverted version of the 74F373
Ordering Code:
Order Number Package Number
Package Description
74F533SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F533SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F533PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation DS009548
www.fairchildsemi.com









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74F533 Даташит, Описание, Даташиты
Unit Loading/Fan Out
Pin Names
Description
D0D7
LE
OE
O0O7
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
Complementary 3-STATE Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
3 mA/24 mA (20 mA)
Function Table
Inputs
LE OE
HL
HL
LL
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
H
D
H
L
X
X
Output
O
L
H
O0
Z
Functional Description
The 74F533 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F533 Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Storage Temperature
65°C to +150°C
Ambient Temperature under Bias
55°C to +125°C
Junction Temperature under Bias
55°C to +150°C
VCC Pin Potential to
Ground Pin
0.5V to +7.0V
Input Voltage (Note 2)
0.5V to +7.0V
Input Current (Note 2)
30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
3-STATE Output
0.5V to VCC
0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
ESD Last Passing Voltage (Min)
4000V
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
VIH
VIL
VCD
VOH
VOL
IIH
IBVI
IBVIT
ICEX
VID
IOD
IIL
IOZH
IOZL
IOS
IZZ
ICCZ
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW Voltage
Input HIGH Current
10% VCC
10% VCC
5% VCC
5% VCC
10% VCC
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown (I/O)
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Min
2.0
2.5
2.4
2.7
2.7
4.75
60
Typ
Max
Units
VCC
Conditions
V Recognized as a HIGH Signal
0.8 V
Recognized as a LOW Signal
1.2
V
Min IIN = −18 mA
IOH = −1 mA
V Min IOH = −3 mA
IOH = −1 mA
IOH = −3 mA
0.5 V Min IOL = 24 mA
5.0 µA Max VIN = 2.7V
7.0 µA Max VIN = 7.0V
0.5 mA Max VIN = 5.5V
50 µA Max VOUT = VCC
V 0.0 IID = 1.9 µA
All Other Pins Grounded
3.75
µA
0.0 VIOD = 150 mV
All Other Pins Grounded
0.6 mA Max VIN = 0.5V
50 µA Max VOUT = 2.7V
50 µA Max VOUT = 0.5V
150 mA Max VOUT = 0V
500 µA 0.0V VOUT = 5.25V
41 61 mA Max VO = HIGH Z
3 www.fairchildsemi.com










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