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PDF 74F544 Data sheet ( Hoja de datos )
| Número de pieza | 74F544 | |
| Descripción | Octal Registered Transceiver | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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April 1988
Revised August 1999
74F544
Octal Registered Transceiver
General Description
The 74F544 octal transceiver contains two sets of D-type
latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. The A outputs are guaranteed to sink 24 mA while the
B outputs are rated for 64 mA. The 74F544 inverts data in
both directions.
Features
s 8-bit octal transceiver
s Back-to-back registers for storage
s Separate controls for data flow in each direction
s A outputs sink 24 mA, B outputs sink 64 mA
Ordering Code:
Order Number Package Number
Package Description
74F544SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F544MSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F544SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009555
www.fairchildsemi.com
1 page  
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA24
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74F544.PDF ] | |
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