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74F574 PDF даташит

Спецификация 74F574 изготовлена ​​​​«Philips» и имеет функцию, называемую «Octal transparent latch 3-State».

Детали детали

Номер произв 74F574
Описание Octal transparent latch 3-State
Производители Philips
логотип Philips логотип 

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74F574 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74F573
Octal transparent latch (3-State)
74F574
Octal transparent latch (3-State)
Product specification
IC15 Data Handbook
1989 Oct 16
Philips
Semiconductors









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74F574 Даташит, Описание, Даташиты
Philips Semiconductors
Latch/flip-flop
Product specification
74F573/74F574
74F573 Octal Transparent Latch (3-State)
74F574 Octal D Flip-Flop (3-State)
FEATURES
74F573 is broadside pinout version of 74F373
74F574 is broadside pinout version of 74F374
Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
Useful as an Input or Output port for Microprocessors
3-State Outputs for Bus interfacing
Common Output Enable
74F563 and 74F564 are inverting version of 74F573 and 74F574
respectively
3-State Outputs glitch free during power-up and power-down
These are High-Speed replacements for N8TS805 and N8TS806
The 74F574 is functionally identical to the 74F374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocesors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE) control gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independently of the latch operation. When OE is Low, the latched
or transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
DESCRIPTION
The 74F573 is an octal transparent latch coupled to eight 3-State
output buffers. The two sections of the device are controlled
independently by Enable (E) and Output Enable (OE) control gates.
The 74F573 is functionally identical to the 74F373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
Enable (E) input is High. The latch remains transparent to the data
input while E is High and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE) controls all eight 3-State buffers
independent to the latch operation. When OE is Low, the latched or
transparent data appears at the outputs. When OE is High, the
outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
TYPE
TYPICAL
PROPAGATION DELAY
74F573
5.0ns
TYPICAL SUPPLY
CURRENT
(TOTAL)
35mA
TYPE
74F574
TYPICAL fMAX
180MHz
TYPICAL SUPPLY
CURRENT
(TOTAL)
50mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
PKG DWG #
20-Pin Plastic DIP
N74F573N, N74F574N SOT146-1
20-Pin Plastic SOL
N74F573D, N74F574D SOT163-1
20-Pin Plastic SSOP
N74F573DB
SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
D0 - D7
Data inputs
E (74F573)
Latch Enable input (active falling edge)
OE Output Enable input (active Low)
CP (74F574) Clock Pulse input (active rising edge)
Q0 - Q7
3-State outputs
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
1989 Oct 16
2 853-0083 97897









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74F574 Даташит, Описание, Даташиты
Philips Semiconductors
Latch/flip-flop
PIN CONFIGURATION – 74F573
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 E
SF01073
LOGIC SYMBOL – 74F573
2 3456789
D0 D1 D2 D3 D4 D5 D6 D7
11 E
1 OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC=Pin 20
GND=Pin 10
19 18 17 16 15 14 13 12
SF01075
LOGIC SYMBOL (IEEE/IEC) – 74F573
1
EN1
11
EN2
2 2D 1
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
SF01077
Product specification
74F573/74F574
PIN CONFIGURATION – 74F574
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 CP
SF01074
LOGIC SYMBOL – 74F574
2 3456789
D0 D1 D2 D3 D4 D5 D6 D7
11 CP
1 OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC=Pin 20
GND=Pin 10
19 18 17 16 15 14 13 12
SF01076
LOGIC SYMBOL (IEEE/IEC) – 74F574
1 EN1
11
C2
2 2D 1
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
SF01078
1989 Oct 16
3










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