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74F579 PDF даташит

Спецификация 74F579 изготовлена ​​​​«Fairchild» и имеет функцию, называемую «8-Bit Bidirectional Binary Counter with 3-STATE Outputs».

Детали детали

Номер произв 74F579
Описание 8-Bit Bidirectional Binary Counter with 3-STATE Outputs
Производители Fairchild
логотип Fairchild логотип 

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74F579 Даташит, Описание, Даташиты
April 1988
Revised August 1999
74F579
8-Bit Bidirectional Binary Counter with 3-STATE Outputs
General Description
The 74F579 is a fully synchronous 8-stage up/down
counter with multiplexed 3-STATE I/O ports for bus-ori-
ented applications. It features a preset capability for pro-
grammable operation, carry lookahead for easy cascading
and a U/D input to control the direction of counting. All state
changes, whether in counting or parallel loading, are initi-
ated by the rising edge of the clock.
Features
s Multiplexed 3-STATE I/O ports
s Built-in lookahead carry capability
s Count frequency 100 MHz typical
s Supply current 75 mA typical
s Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number Package Number
Package Description
74F579SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F579SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F579PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code.
Logic Symbol
Connection Diagram
© 1999 Fairchild Semiconductor Corporation DS009568
www.fairchildsemi.com









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74F579 Даташит, Описание, Даташиты
Unit Loading/Fan Out
Pin Names
I/O0–I/O7
PE
U/D
MR
SR
CEP
CET
CS
OE
CP
TC
Description
Data Inputs or
3-STATE Outputs
Parallel Enable Input (Active LOW)
Up-Down Count Control Input
Master Reset Input (Active LOW)
Synchronous Reset Input (Active LOW)
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Chip Select Input Active (Active LOW)
Output Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Terminal Count Output (Active LOW)
U.L.
HIGH/LOW
3.5/0.333
75/15
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
0.25/0.333
25/12.5
Input IIH/IIL
Output IOH/IOL
70 µA/0.2 mA
3 mA/24 mA
5 µA/0.2 mA
5 µA/0.2 mA
5 µA/0.2 mA
5 µA/0.2 mA
5 µA/0.2 mA
5 µA/0.2 mA
5 µA/0.2 mA
5 µA/0.2 mA
5 µA/0.2 mA
1 mA/5 mA
Function Table
MR SR CS PE CEP CET U/D OE CP
XXHXXXXXX
X X L HXXXHX
XX L HXXX L X
LXXXXXXXX
H L X X X X X X
H H L L X X X X
H H (Not LL) H X X X
H H (Not LL) X H X X
H H (Not LL) L L H X
H H (Not LL) L L L X
Function
I/Oa to I/Oh in High Z (PE Disabled)
I/Oa to I/Oh in High Z
Flip-Flop Outputs Appear on I/O Lines
Asynchronous Reset for all Flip-Flops
Synchronous Reset for all Flip-Flops
Parallel Load all Flip-Flops
Hold
Hold (TC Held HIGH)
Count Up
Count Down
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW to HIGH Clock Transition
Not LL = CS and PE should never both be LOW voltage level at the same time.
www.fairchildsemi.com
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74F579 Даташит, Описание, Даташиты
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
VCC = Pin 16
GND = Pin 6
Detail A
() = Pin Numbers
3
www.fairchildsemi.com










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