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74F646SPC PDF даташит

Спецификация 74F646SPC изготовлена ​​​​«Fairchild» и имеет функцию, называемую «Octal Transceiver/Register with 3-STATE Outputs».

Детали детали

Номер произв 74F646SPC
Описание Octal Transceiver/Register with 3-STATE Outputs
Производители Fairchild
логотип Fairchild логотип 

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74F646SPC Даташит, Описание, Даташиты
March 1988
Revised August 1999
74F646 • 74F646B • 74F648
Octal Transceiver/Register with 3-STATE Outputs
General Description
These devices consist of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control G and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control G is Active LOW.
In the isolation mode (control G HIGH), A data may be
stored in the B register and/or B data may be stored in the
A register.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data
s 74F648 has inverting data paths
s 74F646/74F646B have non-inverting data paths
s 74F646B is a faster version of the 74F646
s 3-STATE outputs
s 300 mil slim DIP
Ordering Code:
Order Number Package Number
Package Description
74F646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F646MSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F646SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F646BSC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F646BSPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F648SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F648SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS009580
www.fairchildsemi.com









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74F646SPC Даташит, Описание, Даташиты
Logic Symbols
74F646/74F646B
IEEE/IEC
74F646/74F646B
74F648
IEEE/IEC
74F648
Connection Diagrams
74F646/74F646B
74F648
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74F646SPC Даташит, Описание, Даташиты
Unit Loading/Fan Out
Pin Names
A0–A7
B0–B7
CPAB, CPBA
SAB, SBA
G
DIR
Description
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Input
Direction Control Input
U.L.
HIGH/LOW
3.5/1.083
600/106.6 (80)
3.5/1.083
600/106.6 (80)
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
Input IIH/IIL
Output IOH/IOL
70 µA/650 µA
12 mA/64 mA (48 mA)
70 µA/650 µA
12 mA/64 mA (48 mA)
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/0.6 mA
Function Table
Inputs
Data I/O (Note 1)
G DIR CPAB CPBA SAB SBA A0–A7 B0–B7
Function
H X H or L H or L X X
Isolation
H X
X X X Input Input Clock An Data into A Register
H X X
XX
Clock Bn Data into B Register
L H X X L X
An to Bn—Real Time (Transparent Mode)
LH
X L X Input Output Clock An Data into A Register
L H H or L X H X
LH
XHX
A Register to Bn (Stored Mode)
Clock An Data into A Register and Output to Bn
L L X X X L
Bn to An—Real Time (Transparent Mode)
L LX
X L Output Input Clock Bn Data into B Register
L L X H or L X H
L LX
XH
B Register to An (Stored Mode)
Clock Bn Data into B Register and Output to An
H = HIGH Voltage Level
L = LOW Voltage Level
X = Irrelevant
= LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
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Номер в каталогеОписаниеПроизводители
74F646SPCOctal Transceiver/Register with 3-STATE OutputsFairchild
Fairchild
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