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74F657 PDF даташит

Спецификация 74F657 изготовлена ​​​​«Philips» и имеет функцию, называемую «Octal transceiver with 8-bit parit generator/checker».

Детали детали

Номер произв 74F657
Описание Octal transceiver with 8-bit parit generator/checker
Производители Philips
логотип Philips логотип 

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74F657 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74F657
Octal transceiver with 8-bit parit
generator/checker
Process specification
IC15 Data Handbook
1990 Jul 30
Philips
Semiconductors









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74F657 Даташит, Описание, Даташиты
Philips Semiconductors
Octal transceiver with 8-bit parity generator/checker
Product specification
74F657
FEATURES
Combines 74F245 and 74F280A functions in one package
High impedance base input for reduced loading (70µA in
high and low states)
Ideal in applications where high output drive and light bus
loading are required (IIL is 70µA vs FAST std of 600µA)
3–state buffer outputs sink 64mA and source 15mA
Input diodes for termination effects
24–pin plastic slim DIP (300mil) package
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F657 is an octal transceiver featuring non–inverting
buffers with 3–state outputs and an 8–bit parity
generator/checker, and is intended for bus–oriented
applications. The buffers have a guaranteed current sinking
capability of 24mA at the A ports and 64mA at the B ports.
The transmit/receive (T/R) input determines the direction of
the data flow through the bidirectional transceivers.
Transmit (active high) enables data from A ports to B ports;
receive (active low) enables data from B ports to A ports.
The output enable (OE) input disables both the A and B ports by
placing them in a high impedance condition when the OE input is
high.
The parity select (ODD/EVEN) input gives the user the option of
odd or even parity systems.
The parity (PARITY) pin is an output from the generator/checker
when transmitting from the port A to B (T/R = high) and an input
when receiving from port B to A port ( T/R = low).
When transmitting (T/R = high) the parity select (ODD/EVEN) input
is set, then the A port data is polled to determined the number of
high bits. The parity (PARITY) output then goes to the logic state
determined by the parity select (ODD/EVEN) setting and by the
number of high bits on port A.
For example, if the parity select (ODD/EVEN) is set low (even
parity), and the number of high bits on port A is odd, then the parity
(PARITY) output will be high, transmitting even parity. If the number
of high bits on port A is even, then the parity (PARITY) output will
be low, keeping even parity.
When in receive mode (T/R = low) the B port is polled to determine
the number of high bits. If parity select (ODD/EVEN) is low (even
parity) and the number of highs on port B is:
(1) odd and the parity (PARITY) input is high, then ERROR will be
high, significantly no error.
(2) even and the parity (PARITY) input is high, then ERROR will be
asserted low, indicating an error.
TYPE
74F657
TYPICAL PROPAGA-
TION DELAY
8.0ns
TYPICAL SUPPLY
CURRENT( TOTAL)
100mA
ORDERING INFORMATION
DESCRIPTION
24–pin plastic slim
DIP (300mil)
24–pin plastic SOL
24–pin plastic SSOP
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
N74F657N
N74F657D
N74F657DB
ORDER CODE
INDUSTRIAL RANGE
VCC = 5V ±10%,
Tamb = –40°C to +85°C
I74F657N
I74F657D
I74F657DB
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 – A7 A ports 3–state inputs
3.5/0.117
70µA/70µA
B0 – B7 B ports 3–state inputs
3.5/0.117
70µA/70µA
PARITY Parity input
3.5/0.117
70µA/70µA
T/R Transmit/receive input
2.0/0.066
40µA/40µA
ODD/EVEN Parity select input
1.0/0.033
20µA/20µA
OE Output enable input (active low)
2.0/0.066
40µA/40µA
A0 – A7 A ports 3–state outputs
150/40
3.0mA/24mA
B0 – B7 B ports 3–state outputs
750/106.7
15mA/64mA
PARITY Parity output
750/106.7
15mA/64mA
ERROR Error output
750/106.7
15mA/64mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
PKG DWG #
SOT222-1
SOT137-1
SOT340-1
90 July 30
2 853 1117 00081









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74F657 Даташит, Описание, Даташиты
Philips Semiconductors
Octal transceiver with 8-bit parity generator/checker
Product specification
74F657
PIN CONFIGURATION
T/R 1
A0 2
A1 3
A2 4
A3 5
A4 6
VCC 7
A5 8
A6 9
A7 10
ODD/EVEN 11
ERROR 12
24 OE
23 B0
22 B1
21 B2
20 B3
19 GND
18 GND
17 B4
16 B5
15 B6
14 B7
13 PARITY
SF00414
IEC/IEEE SYMBOL
24 G3
1 3 EN1/3G5 (REC)
11
3 EN2 (XMIT)
N4
21
23
Z11
3
4
5
6
8
9
10
2
22
21
20
17
16
15
14
11 2 k
. 4, 2
.
.5
18 4, 1
13
12
SF00416
LOGIC SYMBOL
2 3 4 5 6 8 9 10
A0 A1 A2 A3 A4 A5 A6 A7
1 T/R
24 OE
11 ODD/EVEN
PARITY
ERROR
13
12
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 17 16 15 14
VCC = Pin 7
GND = Pin 18, 19
SF00415
90 July 30
3










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