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PDF 74F657 Data sheet ( Hoja de datos )
| Número de pieza | 74F657 | |
| Descripción | Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and 3-STATE Outputs | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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March 1988
Revised August 1999
74F657
Octal Bidirectional Transceiver with
8-Bit Parity Generator/Checker and 3-STATE Outputs
General Description
The 74F657 contains eight non-inverting buffers with 3-
STATE outputs and an 8-bit parity generator/checker. It is
intended for bus-oriented applications. The buffers have a
guaranteed current sinking capability of 24 mA at the A
Port and 64 mA at the B Port.
Features
s 300 Mil 24-pin slimline DIP
s Combines 74F245 and 74F280A functions in one
package
s 3-STATE outputs
s B Outputs sink 64 mA
s 12 mA source current, B side
s Input diodes for termination effects
Ordering Code:
Order Number Package Number
Package Description
75F657SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F657SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009584
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
TA = +25°C
TA = −55°C to +125°C TA = 0°C to +70°C
Symbol
Parameter
VCC = +5.0V
CL = 50 pF
VCC = +5.0V
CL = 50 pF
VCC = +5.0V
CL = 50 pF
Units
Min Typ Max Min Max Min Max
tPLH Propagation Delay
tPHL
An to Bn, Bn to An
tPLH Propagation Delay
tPHL An to Parity
tPLH Propagation Delay
tPHL ODD/EVEN to PARITY
2.5 4.5 8.0 2.5 9.5 2.5 9.0
3.0 4.9 7.5 3.0 8.5 3.0 8.0
6.5
10.1
14.0
5.5
18.0
6.0
16.0
7.0
10.9
15.0
5.5
20.5
6.0
16.5
4.5 7.8 11.0 4.0 14.0 4.0 13.0
4.5 8.8 12.0 4.5 16.5 4.5 13.5
ns
ns
ns
tPLH Propagation Delay
tPHL ODD/EVEN to ERROR
4.5 7.5 11.0 4.0 14.0 4.0 13.0
ns
4.5 8.2 12.0 4.5 16.5 4.5 13.5
tPLH Propagation Delay
tPHL
Bn to ERROR
tPLH Propagation Delay
tPHL PARITY to ERROR
8.0
14.0
20.5
8.0
15.0
21.5
7.0
10.8
15.5
7.5 11.8 16.5
7.5 27.0 7.5 23.0
7.5 28.5 7.5 23.5
6.0 20.0 6.0 17.0
6.5 22.0 7.5 18.5
ns
ns
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
Output Enable Time
OE to An/Bn
Output Disable Time
OE to An/Bn
Output Enable Time
OE to ERROR (Note 3)
3.0 5.0 8.0 2.5 11.0 2.5 9.5
ns
4.0 6.5 10.0 3.5 13.5 3.5 11.0
1.0 4.5 8.0 1.0 9.5 1.0 9.0
ns
1.0 4.9 7.5 1.0 8.5 1.0 8.0
3.0 5.0 8.0 2.5 11.0 2.5 9.5
ns
4.0 7.7 10.0 3.5 13.5 3.5 11.0
tPHZ Output Disable Time
tPLZ OE to ERROR
1.0 4.5 8.0 1.0 9.5 1.0 9.0
ns
1.0 4.9 7.5 1.0 8.5 1.0 8.0
tPZH Output Enable Time
tPZL OE to PARITY
3.0 5.0 8.0 2.5 11.0 2.5 9.5
ns
4.0 7.7 10.0 3.5 13.5 3.5 11.0
tPHZ Output Disable Time
tPLZ OE to PARITY
1.0 4.6 8.0 1.0 9.5 1.0 9.0
ns
1.0 5.1 7.5 1.0 8.5 1.0 8.0
Note 3: These delay times reflect the 3-STATE recovery time only and not the signal time through the buffers or the parity check circuity. To assure VALID
information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to
PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin ≥ (A to PARITY) + (Output
Enable Time).
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74F657.PDF ] | |
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