DataSheet26.com

74F843SC PDF даташит

Спецификация 74F843SC изготовлена ​​​​«Fairchild» и имеет функцию, называемую «9-Bit Transparent Latch».

Детали детали

Номер произв 74F843SC
Описание 9-Bit Transparent Latch
Производители Fairchild
логотип Fairchild логотип 

6 Pages
scroll

No Preview Available !

74F843SC Даташит, Описание, Даташиты
74F843
9-Bit Transparent Latch
General Description
The 74F843 bus interface latch is designed to eliminate the
extra packages required to buffer existing latches and pro-
vide extra data width for wider address/data paths or buses
carrying parity.
Features
s 3-STATE output
January 1988
Revised July 1999
Ordering Code:
Order Number Package Number
Package Description
74F843SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F843SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE
© 1999 Fairchild Semiconductor Corporation DS009453
www.fairchildsemi.com









No Preview Available !

74F843SC Даташит, Описание, Даташиты
Unit Loading/Fan Out
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
D0–D8
OE
Data Inputs
Output Enable Input
1.0/1.0
1.0/1.0
20 µA/0.6 mA
20 µA/0.6 mA
LE Latch Enable
1.0/1.0 20 µA/0.6 mA
CLR
Clear
1.0/1.0 20 µA/0.6 mA
PRE
Preset
1.0/1.0 20 µA/0.6 mA
O0–O8
3-STATE Data Outputs 150/40 3 mA/24 mA
Functional Description
The 74F843 consists of nine D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion. On the LE HIGH-to-LOW transition, the data that
meets the setup times is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state. In addition to
the LE and OE pins, the 74F843 has a Clear (CLR) pin and
a Preset (PRE). These pins are ideal for parity bus interfac-
ing in high performance systems. When CLR is LOW, the
outputs are LOW if OE is LOW. When CLR is HIGH, data
can be entered into the latch. When PRE is LOW, the Out-
puts are HIGH if OE is LOW. Preset overrides CLR.
Function Table
Inputs
CLR PRE OE LE
HHXX
HHHH
HHHH
HHHL
HHLH
HHLH
HHL L
HLLX
LHLX
LLLX
L HH L
HLHL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Internal Output
Function
DQ
O
XX
Z High Z
LL
Z High Z
HH
Z High Z
X NC
Z Latched
LL
L Transparent
HH
H Transparent
X NC NC Latched
XH
H Preset
X L L Clear
XH
H Preset
XL
Z Latched
XH
Z Latched
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2









No Preview Available !

74F843SC Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Storage Temperature
65°C to +150°C
Ambient Temperature under Bias
55°C to +125°C
Junction Temperature under Bias
55°C to +150°C
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
0.5V to +7.0V
0.5V to +7.0V
Input Current (Note 2)
30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
3-STATE Output
0.5V to VCC
0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VCC
Conditions
VIH
VIL
VCD
VOH
VOL
IIH
IBVI
ICEX
VID
IOD
IIL
IOZH
IOZL
IOS
IZZ
ICC
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW Voltage
Input HIGH Current
10% VCC
10% VCC
5% VCC
5% VCC
10% VCC
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
2.0
2.5
2.4
2.7
2.7
4.75
60
V Recognized as a HIGH Signal
0.8 V
Recognized as a LOW Signal
1.2
V
Min IIN = −18 mA
IOH = −1 mA
V Min IOH = −3 mA
IOH = −1 mA
IOH = −3 mA
0.5 V Min IOL = 24 mA
5.0 µA Max VIN = 2.7V
7.0 µA Max VIN = 7.0V
50 µA Max VOUT = VCC
V 0.0 IID = 1.9 µA
All other pins grounded
3.75
µA
0.0 VIOD = 150 mV
All other pins grounded
0.6 mA Max VIN = 0.5V
50 µA Max VOUT = 2.7V
50 µA Max VOUT = 0.5V
150 mA Max VOUT = 0V
500 µA 0.0V VOUT = 5.25V
65 90 mA Max
3 www.fairchildsemi.com










Скачать PDF:

[ 74F843SC.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
74F843SC9-Bit Transparent LatchFairchild
Fairchild
74F843SPC9-Bit Transparent LatchFairchild
Fairchild

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск