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PDF 74FCT273 Data sheet ( Hoja de datos )
| Número de pieza | 74FCT273 | |
| Descripción | Octal D Flip-Flop | |
| Fabricantes | National | |
| Logotipo |  |
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March 1993
54FCT 74FCT273
Octal D Flip-Flop
General Description
The ’FCT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously
The register is fully edge-triggered The state of each D in-
put one setup time before the LOW-to-HIGH clock tran-
sition is transferred to the corresponding flip-flop’s Q out-
put
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements
Features
Y ICC reduced to 40 0 mA
Y Ideal buffer for MOS microprocessor or memory
Y Eight edge-triggered D flip-flops
Y Buffered common clock
Y Buffered asynchronous master reset
Y TTL input and output level compatible
Y TTL levels accept CMOS levels
Y IOL e 48 mA (Com) 32 mA (Mil)
Y NSC 54 74FCT273 is pin and functionally equivalent to
IDT 54 74FCT273
Y Military product compliant to MIL-STD-883 and
Standard Military Drawing 5962-87656
Logic Symbols
IEEE IEC
Connection Diagrams
Pin Assignment
for DIP Flatpak and SOIC
TL F 10146–1
Pin Names
D0 – D7
MR
CP
Q0 – Q7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
TL F 10146 – 2
TL F 10146 – 3
Pin Assignment
for LCC
FACTTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10146
TL F 10146 – 4
RRD-B30M105 Printed in U S A
1 page  
AC Electrical Characteristics
54FCT 74FCT
Symbol
Parameter
TA e a25 C
VCC e 5 0V
Typ
tPHL
tPLH
tPLH
tPHL
tSU
Propagation Delay
Clock to Output
Propagation Delay
MR to Output
Setup Time HIGH
or LOW Data to CP
70
80
15
th Hold Time HIGH
or LOW Data to CP
10
tw Clock Pulse Width
HIGH or LOW
40
tw MR Pulse Width
HIGH or LOW
40
trec Recovery Time
MR to CP
30
fmax
Maximum Clock Frequency
Note 1 Minimum limits are guaranteed but not tested on Propagation Delays
74FCT
TA VCC e Com
RL e 500X
CL e 50 pF
Min Max
2 0 13 0
2 0 13 0
30
20
70
70
40
54FCT
TA VCC e Mil
RL e 500X
CL e 50 pF
Min Max
15 95
1 5 10 5
35
20
50
50
40
90
Units
ns
ns
ns
ns
ns
ns
ns
MHz
Capacitance TA e 25 C f e 1 0 MHz
Symbol
Parameter
Conditions Typ Max Unit
CIN
Input Capacitance VIN e 0V
6 10
COUT Output Capacitance VOUT e 0V 8 12
Note This parameter is guaranteed by characterization data and not tested
pF
pF
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows
74FCT 273 P C QR
Temperature Range Family
74FCT e Commercial TTL-Compatible
54FCT e Military TTL-Compatible
Device Type
Package Code
P e Plastic DIP
D e Ceramic DIP
F e Flatpak
L e Leadless Ceramic Chip Carrier (LCC)
S e Small Outline (SOIC)
Special Variations
X e Devices shipped in 13 reels
QR e Commercial grade device with
burn-in
QB e Military grade with
environmental and burn-in
processing shipped in tubes
Temperature Range
C e Commercial (0 C to a70 C)
M e Military (b55 C to a125 C)
5
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| PDF Descargar | [ Datasheet 74FCT273.PDF ] | |
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