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74FR25900 PDF даташит

Спецификация 74FR25900 изготовлена ​​​​«Fairchild» и имеет функцию, называемую «9-Bit / 3-Port Latchable Datapath Multiplexer with 25W Output Series Resistors».

Детали детали

Номер произв 74FR25900
Описание 9-Bit / 3-Port Latchable Datapath Multiplexer with 25W Output Series Resistors
Производители Fairchild
логотип Fairchild логотип 

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74FR25900 Даташит, Описание, Даташиты
July 1992
Revised August 1999
74FR25900
9-Bit, 3-Port Latchable Datapath Multiplexer
with 25Output Series Resistors
General Description
The 74FR25900 is a data bus multiplexer routing any of
three 9-bit ports to any other one of the three ports. Read-
back of data latched from any port onto itself is also possi-
ble. The 74FR25900 maintains separate control of all latch-
enable, output enable and select inputs for maximum flexi-
bility. PINV allows inversion of the data from the C8 to A8 or
B8 path. This is useful for control of the parity bit in systems
diagnostics.
This device includes 25resistors in series with A and B
Port outputs. Resistors minimize undershoot and ringing
which may damage or corrupt sensitive device inputs
driven by these ports.
Features
s 25series resistors in the port A and B outputs elimi-
nate the need for external resistors when driving MOS
inputs such as DRAM arrays
s 9-bit data ports for systems carrying parity bits
s Readback capability for system self checks.
s Independent control lines for maximum flexibility
s Guaranteed multiple output switching and 250 pF load
delays
s Outputs optimized for dynamic bus drive capability
s PINV parity control facilitates system diagnostics
s 74FR900 option available without output series resistors
Ordering Code:
Order Number Package Number
Package Description
74FR25900SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Description
Pin Names
LExx
OEx
PINV
S0, S1
A0–A8
B0–B8
C0–C8
Description
Latch Enable Inputs
Output Enable Inputs
Parity Invert Input
Select Inputs
Port A Inputs or 3-STATE Outputs
Port B Inputs or 3-STATE Outputs
Port C Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011500
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74FR25900 Даташит, Описание, Даташиты
Functional Description
The 74FR25900 allows 9-bit data to be transferred from
any of three 9-bit I/O ports to either of the two remaining
I/O ports. The device employs latches in all paths for either
transparent or synchronous operation. Readback capability
from any port to itself is also possible.
Data transfer within the 74FR25900 is controlled through
use of the select (S0 and S1) and output-enable (OEA, OEB
and OEC) inputs as described in Table 1. Additional control
is available by use of the latch-enable inputs (LEAC, LECA,
LEBC, LECB) allowing either synchronous or transparent
transfers (see Table 2). Table 1 indicates several readback
conditions. By latching data on a given port and initiating
the readback control configuration, previous data may be
read for system verification or diagnostics. This mode may
be useful in implementing system diagnostics.
Data at the port to be readback must be latched prior to
enabling the outputs on that port. If this is not done, a
closed data loop will result causing possible data integrity
problems. Note that the A and B Ports allow readback with-
out affecting any other port. C Port, however, requires inter-
ruption of either A or B Ports to complete its readback path.
PINV controls inversion of the C8 bit. A LOW on PINV
allows C8 data to pass unaltered. A HIGH causes inversion
of the data. See Table 3. This feature allows forcing of par-
ity errors for use in system diagnostics. This is particularly
helpful in 486 processor designs as the 486 does not pro-
vide odd/even parity selection internally.
TABLE 1. Datapath Control
Inputs
S0 S1 OEA OEB OEC
Function
LXH
L
L Port A to Port C
L L H H H Port A to Port B
LO H
H
L Port A to B+C
HL
L
L
H Port B to Port A
HX H
L
L Port B to Port C
H O L L L Port B to A+C
X H L L H Port C to Port A
X H H H H Port C to Port B
X H L H H Port C to A+B
XX H
L
H Outputs Disabled
L L L X X (Readback to A)
(Note 1)
L H L X L (Readback to A or C)
(Note 1)
H L X H X (Readback to B)
(Note 1)
HH X
H
L (Readback to B or C)
(Note 1)
Note 1: Readback operation in latched mode only. Transparent operation
could result in unpredictable results.
TABLE 2. Latch-Enable Control
LExx
L
L
H
Input
L
H
X
Output
L
H
Q0
TABLE 3. PINV Control
PINV
L
L
H
H
C8 A8 or B8
LL
HH
LH
HL
Key:
L = LOW Voltage
H = HIGH Voltage Level
Q0 = Output state prior to LExx LOW-to-HIGH transition
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74FR25900 Даташит, Описание, Даташиты
Logic Diagram
Schematic of A and B Port Outputs
3 www.fairchildsemi.com










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Номер в каталогеОписаниеПроизводители
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74FR25900SSC9-Bit / 3-Port Latchable Datapath Multiplexer with 25W Output Series ResistorsFairchild
Fairchild

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