DataSheet26.com

74FR900 PDF даташит

Спецификация 74FR900 изготовлена ​​​​«Fairchild» и имеет функцию, называемую «9-Bit / 3-Port Latchable Datapath Multiplexer».

Детали детали

Номер произв 74FR900
Описание 9-Bit / 3-Port Latchable Datapath Multiplexer
Производители Fairchild
логотип Fairchild логотип 

6 Pages
scroll

No Preview Available !

74FR900 Даташит, Описание, Даташиты
May 1992
Revised August 1999
74FR900
9-Bit, 3-Port Latchable Datapath Multiplexer
General Description
The 74FR900 is a data bus multiplexer routing any of three
9-bit ports to any other one of the three ports. Readback of
data latched from any port onto itself is also possible. The
74FR900 maintains separate control of all latch-enable,
output enable and select inputs for maximum flexibility.
PINV allows inversion of the data from the C8 to A8 or B8
path. This is useful for control of the parity bit in systems
diagnostics.
Fairchild’s 74FR25900 includes 25resistors in series with
port A and B outputs. Resistors minimize undershoot and
ringing which may damage or corrupt sensitive device
inputs driven by these ports.
Features
s 9-bit data ports for systems carrying parity bits
s Readback capability for system self checks.
s Independent control lines for maximum flexibility
s Guaranteed multiple output switching and 250 pF load
delays
s Outputs optimized for dynamic bus drive capability
s PINV parity control facilitates system diagnostics
s FR25900 resistor option for driving MOS inputs such as
DRAM arrays
Ordering Code:
Order Number Package Number
Package Description
74FR900SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Description
Pin Names
LExx
OEx
PINV
S0, S1
A0–A8
B0–B8
C0–C8
Description
Latch Enable Inputs
Output Enable Inputs
Parity Invert Input
Select Inputs
Port A Inputs or 3-STATE Outputs
Port B Inputs or 3-STATE Outputs
Port C Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS010990
www.fairchildsemi.com









No Preview Available !

74FR900 Даташит, Описание, Даташиты
Functional Description
The 74FR900 allows 9-bit data to be transferred from any
of three 9-bit I/O ports to either of the two remaining I/O
ports. The device employs latches in all paths for either
transparent or synchronous operation. Readback capability
from any port to itself is also possible.
Data transfer within the 74FR900 is controlled through use
of the select (S0 and S1) and output-enable (OEA, OEB and
OEC) inputs as described in Table 1. Additional control is
available by use of the latch-enable inputs (LEAC, LECA,
LEBC, LECB) allowing either synchronous or transparent
transfers (see Table 2). Table 1 indicates several readback
conditions. By latching data on a given port and initiating
the readback control configuration, previous data may be
read for system verification or diagnostics. This mode may
be useful in implementing system diagnostics.
Data at the port to be readback must be latched prior to
enabling the outputs on that port. If this is not done, a
closed data loop will result causing possible data integrity
problems. Note that the A and B ports allow readback with-
out affecting any other port. Port C, however, requires inter-
ruption of either port A or B to complete its readback path.
PINV controls inversion of the C8 bit. A low on PINV allows
C8 data to pass unaltered. A high causes inversion of the
data. See Table 3. This feature allows forcing of parity
errors for use in system diagnostics. This is particularly
helpful in 486 processor designs as the 486 does not pro-
vide odd/even parity selection internally.
TABLE 1. Datapath Control
Inputs
S0 S1 OEA OEB OEC
Function
L X H L L Port A to Port C
L L H H H Port A to Port B
L O H H L Port A to B+C
H L L L H Port B to Port A
H X H L L Port B to Port C
H O L L L Port B to A+C
X H L L H Port C to Port A
X H H H H Port C to Port B
X H L H H Port C to A+B
X X H L H Outputs Disabled
L L L X X (Readback to A)
(Note 1)
L H L X L (Readback to A or C)
(Note 1)
H L X H X (Readback to B)
(Note 1)
H H X H L (Readback to B or C)
(Note 1)
Note 1: Readback operation in latched mode only. Transparent operation
could result in unpredictable results.
TABLE 2. Latch-Enable Control
LExx
L
L
H
Input
L
H
X
Output
L
H
Q0
L = LOW Voltage
H = HIGH Voltage Level
TABLE 3. PINV Control
PINV
L
L
H
H
C8
L
H
L
H
A8 or B8
L
H
H
L
Q0 = Output state prior to LExx LOW-to-HIGH transition
Logic Diagram
www.fairchildsemi.com
2









No Preview Available !

74FR900 Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 2)
Storage Temperature
65°C to +150°C
Ambient Temperature under Bias
55°C to +125°C
Junction Temperature under Bias
55°C to +150°C
VCC Pin Potential to Ground Pin
Input Voltage (Note 3)
0.5V to +7.0V
0.5V to +7.0V
Input Current (Note 3)
30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
3-STATE Output
0.5V to VCC
0.5V to +5.5V
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
ESD Last Passing Voltage (Min)
4000V
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
VIH Input HIGH Voltage
VIL Input LOW Voltage
VCD Input Clamp Diode Voltage
VOH Output HIGH Voltage
VOL
IIH
IBVI
IBVIT
IIL
VID
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
Input Leakage Test
IOD Output Circuit Leakage Test
IIH + IOZH Output Leakage Current
IIIL + IOZL Output Leakage Current
IOS Output Short Circuit Current
ICEX
Output HIGH Leakage Current
IZZ Bus Drainage Test
ICCH
Power Supply Current
ICCL Power Supply Current
ICCZ
Power Supply Current
Note 4: 2 ports active only
Min
Typ
Max
Units
VCC
Conditions
2.0 V Recognized HIGH Signal
0.8 V
Recognized LOW Signal
1.2
V
Min IIN = −18 mA
2.4 V Min IOH = −3 mA (An, Bn, Cn)
2.0 V Min IOH = −15 mA (An, Bn, Cn)
0.50
V
Min IOL = 24 mA (An, Bn, Cn)
5 µA Max VIN = 2.7V (Control Inputs)
7 µA Max VIN = 7.0V (Control Inputs)
100 µA Max VIN = 5.5V (An, Bn, Cn)
4.75
150 µA Max VIN = 0.5V (Control Inputs)
V 0.0 IID = 1.9 µA,
All Other Pins Grounded
3.75
V
0.0 VIOD = 150 mV,
All Other Pins Grounded
25 µA Max VOUT =2.7V (An, Bn, Cn)
150 µA Max VOUT = 0.5V (An, Bn, Cn)
100
225 mA Max VOUT = 0.0V (An, Bn, Cn)
50 µA Max VOUT = VCC (An, Bn, Cn)
100 µA 0.0 VOUT = 5.25V (An, Bn, Cn)
115 150 mA Max All Outputs HIGH (Note 4)
170 200 mA Max All Outputs LOW (Note 4)
147 175 mA Max Outputs in 3-STATE
3 www.fairchildsemi.com










Скачать PDF:

[ 74FR900.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
74FR9009-Bit / 3-Port Latchable Datapath MultiplexerFairchild
Fairchild
74FR900SSC9-Bit / 3-Port Latchable Datapath MultiplexerFairchild
Fairchild

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск