74HC175D PDF даташит
Спецификация 74HC175D изготовлена «Philips» и имеет функцию, называемую «Quad D-type flip-flop with reset positive-edge trigger». |
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Детали детали
Номер произв | 74HC175D |
Описание | Quad D-type flip-flop with reset positive-edge trigger |
Производители | Philips |
логотип |
13 Pages
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT175
Quad D-type flip-flop with reset;
positive-edge trigger
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1998 Jul 08
No Preview Available ! |
Philips Semiconductors
Product specification
Quad D-type flip-flop with reset; positive-edge trigger 74HC/HCT175
FEATURES
• Four edge-triggered D flip-flops
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT175 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT175 have four edge-triggered, D-type
flip-flops with individual D inputs and both Q and Q
outputs.
The common clock (CP) and master reset (MR) inputs load
and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
All Qn outputs will be forced LOW independently of clock
or data inputs by a LOW voltage level on the MR input.
The device is useful for applications where both the true
and complement outputs are required and the clock and
master reset are common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL PARAMETER
CONDITIONS
tPHL propagation delay
CL = 15 pF; VCC = 5 V
CP to Qn, Qn
MR to Qn
tPLH propagation delay
CP to Qn, Qn
MR to Qn
fmax maximum clock frequency
CI input capacitance
CPD power dissipation capacitance per flip-flop notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
TYPICAL
HC HCT
UNIT
17 16 ns
15 19 ns
17 16 ns
15 16 ns
83 54 MHz
3.5 3.5 pF
32 34 pF
1998 Jul 08
2
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Philips Semiconductors
Quad D-type flip-flop with reset; positive-edge trigger
Product specification
74HC/HCT175
ORDERING INFORMATION
TYPE
NUMBER
74HC175N;
74HCT175N
74HC175D;
74HCT175D
74HC175DB;
74HCT175DB
74HC175PW;
74HCT175PW
NAME
DIP16
PACKAGE
DESCRIPTION
plastic dual in-line package; 16 leads (300 mil); long body
SO16 plastic small outline package; 16 leads; body width 3.9 mm
SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
VERSION
SOT38-1
SOT109-1
SOT338-1
SOT403-1
PIN DESCRIPTION
PIN NO.
1
2, 7, 10, 15
3, 6, 11, 14
4, 5, 12, 13
8
9
16
SYMBOL
MR
Q0 to Q3
Q0 to Q3
D0 to D3
GND
CP
VCC
NAME AND FUNCTION
master reset input (active LOW)
flip-flop outputs
complementary flip-flop outputs
data inputs
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jul 08
3
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Номер в каталоге | Описание | Производители |
74HC175 | Quad D-type flip-flop with reset positive-edge trigger | Philips |
74HC175AP | QUAD D - TYPE FLIP FLOP WITH CLEAR | Toshiba Semiconductor |
74HC175D | Quad D-type flip-flop with reset positive-edge trigger | Philips |
74HC175DB | Quad D-type flip-flop with reset positive-edge trigger | Philips |
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