74HC238 PDF даташит
Спецификация 74HC238 изготовлена «Philips» и имеет функцию, называемую «3-to-8 line decoder/demultiplexer». |
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Детали детали
Номер произв | 74HC238 |
Описание | 3-to-8 line decoder/demultiplexer |
Производители | Philips |
логотип |
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT238
3-to-8 line decoder/demultiplexer
Product specification
File under Integrated Circuits, IC06
December 1990
No Preview Available ! |
Philips Semiconductors
3-to-8 line decoder/demultiplexer
Product specification
74HC/HCT238
FEATURES
• Demultiplexing capability
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Active HIGH mutually exclusive outputs
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT238 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT238 decoders accept three binary
weighted address inputs (A0, A1, A2) and when enabled,
provide 8 mutually exclusive active HIGH outputs
(Y0 to Y7).
The “238” features three enable inputs: two active LOW
(E1 and E2) and one active HIGH (E3). Every output will be
LOW unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel
expansion of the “238” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “238” ICs and one inverter.
The “238” can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data
input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their
appropriate active HIGH or LOW state.
The “238” is identical to the “138” but has non-inverting
outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL PARAMETER
CONDITIONS
tPHL/ tPLH
CI
CPD
propagation delay
An to Yn
E3 to Yn
En to Yn
input capacitance
power dissipation capacitance per package
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
TYPICAL
HC HCT
14 18
16 20
17 21
3.5 3.5
72 76
UNIT
ns
ns
ns
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
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Philips Semiconductors
3-to-8 line decoder/demultiplexer
PIN DESCRIPTION
PIN NO.
1, 2, 3
4, 5
6
8
15, 14, 13, 12, 11, 10, 9, 7
16
SYMBOL
A0 to A2
E1, E2
E3
GND
Y0 to Y7
VCC
NAME AND FUNCTION
address inputs
enable inputs (active LOW)
enable input (active HIGH)
ground (0 V)
outputs (active HIGH)
positive supply voltage
Product specification
74HC/HCT238
Fig.1 Pin configuration.
Fig.2 Logic symbol.
(a) (b)
Fig.3 IEC logic symbol.
December 1990
3
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