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74HC257N PDF даташит

Спецификация 74HC257N изготовлена ​​​​«Philips» и имеет функцию, называемую «Quad 2-input multiplexer 3-state».

Детали детали

Номер произв 74HC257N
Описание Quad 2-input multiplexer 3-state
Производители Philips
логотип Philips логотип 

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74HC257N Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT257
Quad 2-input multiplexer; 3-state
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Sep 30









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74HC257N Даташит, Описание, Даташиты
Philips Semiconductors
Quad 2-input multiplexer; 3-state
Product specification
74HC/HCT257
FEATURES
Non-inverting data path
3-state outputs interface directly with system bus
Output capability: bus driver
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT257 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT257 have four identical 2-input multiplexers
with 3-state outputs, which select 4 bits of data from two
sources and are controlled by a common data select
input (S).
The data inputs from source 0 (1I0 to 4I0) are selected
when input S is LOW and the data inputs from source 1
(1I1 to 4I1) are selected when S is HIGH. Data appears at
the outputs (1Y to 4Y) in true (non-inverting) form from the
selected inputs.
The “257” is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to S. The outputs
are forced to a high impedance OFF-state when OE is
HIGH.
The logic equations for the outputs are:
1Y = OE.(1I1.S + 1I0.S)
2Y = OE.(2I1.S + 2I0.S)
3Y = OE.(3I1.S + 3I0.S)
4Y = OE.(4I1.S + 4I0.S)
The “257” is identical to the “258” but has non-inverting
(true) outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
HC HCT
tPHL/ tPLH
CI
CPD
propagation delay
nI0, nI1 to nY
S to nY
CL = 15 pF; VCC = 5 V
11
14
input capacitance
3.5
power dissipation capacitance per multiplexer notes 1 and 2
45
13
17
3.5
45
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
UNIT
ns
ns
pF
pF
1998 Sep 30
2









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74HC257N Даташит, Описание, Даташиты
Philips Semiconductors
Quad 2-input multiplexer; 3-state
Product specification
74HC/HCT257
ORDERING INFORMATION
TYPE
NUMBER
74HC257N;
74HCT257N
74HC257D;
74HCT257D
74HC257DB;
74HCT257DB
74HC257PW;
74HCT257PW
NAME
DIP16
PACKAGE
DESCRIPTION
plastic dual in-line package; 16 leads (300 mil); long body
SO16 plastic small outline package; 16 leads; body width 3.9 mm
SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm
TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm
VERSION
SOT38-1
SOT109-1
SOT338-1
SOT403-1
PIN DESCRIPTION
PIN NO.
1
2, 5, 11, 14
3, 6, 10, 13
4, 7, 9, 12
8
15
16
SYMBOL
S
1I0 to 4I0
1I1 to 4I1
1Y to 4Y
GND
OE
VCC
NAME AND FUNCTION
common data select input
data inputs from source 0
data inputs from source 1
3-state multiplexer outputs
ground (0 V)
3-state output enable input (active LOW)
positive supply voltage
fpage
S1
1I0 2
1I1 3
1Y 4
2I0 5
2I1 6
2Y 7
GND 8
16 VCC
15 OE
14 4I0
13 4I1
257
12 4Y
11 3I0
10 3I1
9 3Y
MLB311
fpage
1
S
2 1I0
1Y 4
3 1I1
5 2I0
6 2I1
2Y 7
11 3I0
10 3I1
3Y 9
14 4I0
13 4I1
4Y 12
15 OE
MGA835
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Sep 30
3










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