74HC393 PDF даташит
Спецификация 74HC393 изготовлена «Philips» и имеет функцию, называемую «Dual 4-bit binary ripple counter». |
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Детали детали
Номер произв | 74HC393 |
Описание | Dual 4-bit binary ripple counter |
Производители | Philips |
логотип |
7 Pages
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT393
Dual 4-bit binary ripple counter
Product specification
File under Integrated Circuits, IC06
December 1990
No Preview Available ! |
Philips Semiconductors
Dual 4-bit binary ripple counter
Product specification
74HC/HCT393
FEATURES
• Two 4-bit binary counters with individual clocks
• Divide-by any binary module up to 28 in one package
• Two master resets to clear each 4-bit counter
individually
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT393 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT393 are 4-bit binary ripple counters with
separate clocks (1CP and 2 CP) and master reset (1MR
and 2MR) inputs to each counter. The operation of each
half of the “393” is the same as the “93” except no external
clock connections are required.
The counters are triggered by a HIGH-to-LOW transition of
the clock inputs. The counter outputs are internally
connected to provide clock inputs to succeeding stages.
The outputs of the ripple counter do not change
synchronously and should not be used for high-speed
address decoding.
The master resets are active-HIGH asynchronous inputs
to each 4-bit counter identified by the “1” and “2” in the pin
description.
A HIGH level on the nMR input overrides the clock and
sets the outputs LOW.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/ tPLH
fmax
CI
CPD
propagation delay
nCP to nQ0
nQ to nQn+1
nMR to nQn
maximum clock frequency
input capacitance
power dissipation capacitance per counter
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
TYPICAL
HC HCT
UNIT
12 20 ns
5 6 ns
11 15 ns
99 53 MHz
3.5 3.5 pF
23 25 pF
December 1990
2
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Philips Semiconductors
Dual 4-bit binary ripple counter
PIN DESCRIPTION
PIN NO.
1, 13
2, 12
3, 4, 5, 6, 11, 10, 9, 8
7
14
SYMBOL
1CP, 2CP
1MR, 2MR
1Q0 to 1Q3, 2Q0 to 2Q3
GND
VCC
Product specification
74HC/HCT393
NAME AND FUNCTION
clock inputs (HIGH-to-LOW, edge-triggered)
asynchronous master reset inputs (active HIGH)
flip-flop outputs
ground (0 V)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
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