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PDF 74HC4046 Data sheet ( Hoja de datos )
| Número de pieza | 74HC4046 | |
| Descripción | Phase-Locked Loop | |
| Fabricantes | ON | |
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MC74HC4046A
Phase-Locked Loop
High–Performance Silicon–Gate CMOS
The MC74HC4046A is similar in function to the MC14046 Metal
gate CMOS device. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC4046A phase–locked loop contains three phase
comparators, a voltage–controlled oscillator (VCO) and unity gain
op–amp DEMOUT. The comparators have two common signal inputs,
COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly
coupled to large voltage signals, or indirectly coupled (with a series
capacitor to small voltage signals). The self–bias circuit adjusts small
voltage signals in the linear region of the amplifier. Phase comparator
1 (an exclusive OR gate) provides a digital error signal PC1OUT and
maintains 90 degrees phase shift at the center frequency between
SIGIN and COMPIN signals (both at 50% duty cycle). Phase
comparator 2 (with leading–edge sensing logic) provides digital error
signals PC2OUT and PCPOUT and maintains a 0 degree phase shift
between SIGIN and COMPIN signals (duty cycle is immaterial). The
linear VCO produces an output signal VCOOUT whose frequency is
determined by the voltage of input VCOIN signal and the capacitor
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain
op–amp output DEMOUT with an external resistor is used where the
VCOIN signal is needed but no loading can be tolerated. The inhibit
input, when high, disables the VCO and all op–amps to minimize
standby power consumption.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage–to–frequency conversion and motor speed control.
• Output Drive Capability: 10 LSTTL Loads
• Low Power Consumption Characteristic of CMOS Devices
• Operating Speeds Similar to LSTTL
• Wide Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 µA Maximum (except SIGIN and COMPIN)
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Low Quiescent Current: 80 µA Maximum (VCO disabled)
• High Noise Immunity Characteristic of CMOS Devices
• Diode Protection on all Inputs
• Chip Complexity: 279 FETs or 70 Equivalent Gates
http://onsemi.com
16
1
16
1
PDIP–16
N SUFFIX
CASE 648
SO–16
D SUFFIX
CASE 751B
MARKING
DIAGRAMS
16
MC74HC4046AN
AWLYYWW
1
16
HC4046A
AWLYWW
1
16
16
1
16
1
TSSOP–16
DT SUFFIX
CASE 948F
HC40
46A
ALYW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
74HC4046B
AWLYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package Shipping
MC74HC4046AN
PDIP–16 2000 / Box
MC74HC4046AD
SOIC–16 48 / Rail
MC74HC4046ADR2
SOIC–16 2500 / Reel
MC74HC4046AF
SOIC–EIAJ See Note
MC74HC4046AFEL
SOIC–EIAJ SNeOe TNAoGte
1. For ordering information on the EIAJ verNsOionToAfGthe
SOIC packages, please contact your local ON
Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 7
1
Publication Order Number:
MC74HC4046A/D
1 page  
MC74HC4046A
[VCO Section]
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
VCC
Volts
– 55 to 25_C ≤ 85°C
Min Max Min Max
≤ 125°C
Min Max
Unit
∆f/T Frequency Stability with
Temperature Changes
(Figure 13A, B, C)
3.0
4.5
6.0
%/K
fo VCO Center Frequency
(Duty Factor = 50%)
(Figure 14A, B, C, D)
3.0 3
4.5 11
6.0 13
MHz
∆fVCO VCO Frequency Linearity
3.0 See Figures 15A, B, C %
4.5
6.0
∂ VCO Duty Factor at VCOOUT
3.0 Typical 50% %
4.5
6.0
[Demodulator Section]
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
RS Resistor Range
VOFF
Offset Voltage
VCOIN to VDEMOUT
RD Dynamic Output
Resistance at DEMOUT
Test Conditions
At RS > 300 kΩ the
Leakage Current can
Influence VDEMOUT
Vi = VVCOIN = 1/2 VCC;
Values taken over RS
Range.
VDEMOUT = 1/2 VCC
Guaranteed Limit
VCC
Volts
– 55 to 25_C ≤ 85°C
Min Max Min Max
≤ 125°C
Min Max
Unit
3.0 50 300
4.5 50 300
6.0 50 300
kΩ
3.0
See Figure 12
mV
4.5
6.0
3.0 Typical 25 Ω Ω
4.5
6.0
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5
5 Page 
MC74HC4046A
23
21 VCC = 6.0 V
19
17 VCC = 4.5 V
15
13
11 VCC = 3.0 V
9
R1 = 3.0 kΩ
C1 = 39 pF
7.0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VVCOIN (V)
Figure 14A. VCO Frequency (fVCO) as a Function
of the VCO Input Voltage (VVCOIN)
70
VCC = 4.5 V VCC = 6.0 V
60
50 VCC = 3.0 V
40
30
20
10
0
0
R1 = 3.0 kΩ
C1 = 0.1 µF
0.5 1.0 1.5 2.0 2.5 3.0
VVCOIN (V)
3.5 4.0
Figure 14B. VCO Frequency (fVCO) as a Function
of the VCO Input Voltage (VVCOIN)
2.0
VCC = 4.5 V
VCC = 3.0 V
VCC = 6.0 V
1.0
R1 = 300 kΩ
C1 = 39 pF
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VVCOIN (V)
Figure 14C. VCO Frequency (fVCO) as a Function
of the VCO Input Voltage (VVCOIN)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
VCC = 6.0 V
VCC = 4.5 V
VCC = 3.0 V
R1 = 300 kΩ
C1 = 0.1 µF
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VVCOIN (V)
Figure 14D. VCO Frequency (fVCO) as a Function
of the VCO Input Voltage (VVCOIN)
2.0
VCC=
4.5 V
1.0
6.0 V
3.0 V
0
4.5 V
6.0 V
–1.0
3.0 V
–2.0 100
C1 = 1.0 µF
C1 = 39 pF
101
R1 (kΩ)
R2 = ∞; ∆V = 0.5 V
102 103
Figure 15A. Frequency Linearity versus
R1, C1 and VCC
f2
f0
f0′
f1
MIN 1/2 VCC MAX
∆V = 0.5 V OVER THE VCC RANGE:
FOR VCO LINEARITY
f0′ = (f1 + f2) / 2
LINEARITY = (f0′ – f0) / f0′) x 100%
Figure 15B. Definition of VCO Frequency Linearity
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11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 74HC4046.PDF ] | |
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