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74HC4094 PDF даташит

Спецификация 74HC4094 изготовлена ​​​​«Philips» и имеет функцию, называемую «8-stage shift-and-store bus register».

Детали детали

Номер произв 74HC4094
Описание 8-stage shift-and-store bus register
Производители Philips
логотип Philips логотип 

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74HC4094 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4094
8-stage shift-and-store bus register
Product specification
File under Integrated Circuits, IC06
December 1990









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74HC4094 Даташит, Описание, Даташиты
Philips Semiconductors
8-stage shift-and-store bus register
Product specification
74HC/HCT4094
FEATURES
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4094 are high-speed Si-gate CMOS
devices and are pin compatible with the “4094” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4094 are 8-stage serial shift registers
having a storage latch associated with each stage for
strobing data from the serial input (D) to the parallel
buffered 3-state outputs (QP0 to QP7). The parallel outputs
may be connected directly to common bus lines.
Data is shifted on the positive-going clock (CP) transitions.
The data in each shift register stage is transferred to the
storage register when the strobe input (STR) is HIGH.
Data in the storage register appears at the outputs
whenever the output enable input (OE) signal is HIGH.
Two serial outputs (QS1 and QS2) are available for
cascading a number of “4094” devices. Data is available at
QS1 on the positive-going clock edges to allow high-speed
operation in cascaded systems in which the clock rise time
is fast. The same serial information is available at QS2 on
the next negative-going clock edge and is for cascading
“4094” devices when the clock rise time is slow.
APPLICATIONS
Serial-to-parallel data conversion
Remote control holding register
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/ tPLH
fmax
CI
CPD
propagation delay
CP to QS1
CP to QS2
CP to QPn
STR to QPn
maximum clock frequency
input capacitance
power dissipation capacitance per package
CL = 15 pF; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
(CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
TYPICAL
HC HCT
15 19
13 18
20 21
18 19
95 86
3.5 3.5
83 92
UNIT
ns
ns
ns
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2









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74HC4094 Даташит, Описание, Даташиты
Philips Semiconductors
8-stage shift-and-store bus register
PIN DESCRIPTION
PIN NO.
1
2
3
4, 5, 6, 7,14, 13, 12, 11
8
9, 10
15
16
SYMBOL
STR
D
CP
QP0 to QP7
GND
QS1, QS2
OE
VCC
NAME AND FUNCTION
strobe input
serial input
clock input
parallel outputs
ground (0 V)
serial outputs
output enable input
positive supply voltage
Product specification
74HC/HCT4094
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3










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