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74HC4094 PDF даташит

Спецификация 74HC4094 изготовлена ​​​​«System Logic» и имеет функцию, называемую «8-Bit Serial-Input Shift Register With Latched 3-State Outputs(High-Performance Silicon-Gate CMOS)».

Детали детали

Номер произв 74HC4094
Описание 8-Bit Serial-Input Shift Register With Latched 3-State Outputs(High-Performance Silicon-Gate CMOS)
Производители System Logic
логотип System Logic логотип 

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74HC4094 Даташит, Описание, Даташиты
SL74HC4094
8-Bit Serial-Input Shift Register With Latched
3-State Outputs
High-Performance Silicon-Gate CMOS
The SL74HC4094 is identical in pinout to the LS/ALS4094. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of an 8-bit shift register and 8-bit D-type latch
with three-state parallel outputs. Data is shifted serially through the
shift register on the positive going transition of the clock input signal.
The output of the last stage SQH can be used to cascade several
devices.
Data on the SQH output is transferred to a second output (SQH’) on
the following negative transition of the clock input signal. The data of
each stage of the shift register is provided with a latch, which latches
data on the negative going transition of the Strobe input signal. When
the Strobe input is held high, data propagates through the latch to a 3-
state output buffer.
This buffer is enabled when Output Enable input is taken high.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC4094N Plastic
SL74HC4094D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
SLS
System Logic
Semiconductor
FUNCTION TABLE
Inputs
Parallel Serial
Outputs Outputs
Clock Output Strobe A QA QN SQH SQH
Enable
L X X Z Z Q6 NC
L X X Z Z NC SQH
H L X NC NC Q6 NC
HH
HH
HX
NC = No Change
Z = high impedance
X = don’t care
L L QN-1 Q6 NC
H H QN-1 Q6 NC
X NC NC NC SQH









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74HC4094 Даташит, Описание, Даташиты
SL74HC4094
MAXIMUM RATINGS*
Symbol
VCC
VIN
VOUT
IIN
IOUT
ICC
PD
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
±25
±50
750
500
Tstg Storage Temperature
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
-65 to +150
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mA
mA
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
VIN, VOUT
TA
tr, tf
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min Max Unit
2.0 6.0
V
0 VCC
-55 +125
V
°C
0 1000 ns
0 500
0 400
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND(VIN or VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
SLS
System Logic
Semiconductor









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74HC4094 Даташит, Описание, Даташиты
SL74HC4094
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VIH Minimum High-Level VOUT= 0.1 V or VCC-0.1 V
Input Voltage
IOUT≤ 20 µA
VIL Maximum Low -Level VOUT=0.1 V or VCC-0.1 V
Input Voltage
IOUT ≤ 20 µA
VOH Minimum High-Level VIN=VIH or VIL
Output Voltage
IOUT ≤ 20 µA
VIN= VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
VOL Maximum Low-Level VIN=VIH or VIL
Output Voltage
IOUT ≤ 20 µA
VIN= VIH or VIL
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
IIN Maximum Input
Leakage Current
VIN=VCC or GND
IOZ Maximum Three-State Output in High-Impedance
Leakage Current
State
VIN= VIL or VIH
VOUT=VCC or GND
ICC Maximum Quiescent VIN=VCC or GND
Supply Current
IOUT=0µA
(per Package)
VCC Guaranteed Limit
V 25 °C 85 125 Unit
to °C °C
-55°C
2.0 1.5 1.5 1.5
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
V
2.0 0.5 0.5 0.5
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
V
2.0 1.9
4.5 4.4
6.0 5.9
1.9 1.9
4.4 4.4
5.9 5.9
V
4.5 3.98 3.84 3.7
6.0 5.48 5.34 5.2
2.0 0.1
4.5 0.1
6.0 0.1
0.1 0.1
0.1 0.1
0.1 0.1
V
4.5 0.26 0.33 0.4
6.0 0.26 0.33 0.4
6.0 ±0.1 ±1.0 ±1.0 µA
6.0 ±0.5 ±5.0 ±10 µA
6.0 4.0
40 160 µA
SLS
System Logic
Semiconductor










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