74HC564 PDF даташит
Спецификация 74HC564 изготовлена «Philips» и имеет функцию, называемую «Octal D-type flip-flop positive-edge trigger 3-state inverting». |
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Детали детали
Номер произв | 74HC564 |
Описание | Octal D-type flip-flop positive-edge trigger 3-state inverting |
Производители | Philips |
логотип |
7 Pages
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT564
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
Product specification
File under Integrated Circuits, IC06
December 1990
No Preview Available ! |
Philips Semiconductors
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
Product specification
74HC/HCT564
FEATURES
• 3-state inverting outputs for bus oriented applications
• 8-bit positive-edge triggered register
• Common 3-state output enable input
• Independent register and 3-state buffer operation
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT564 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT564 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable (OE) input are common to all
flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are
available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The “564” is functionally identical to the “574” but has
inverting outputs. The “564” is functionally identical to the
“534”, but has a different pinning.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
tPHL/ tPLH
fmax
CI
CPD
PARAMETER
propagation delay CP to Qn
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
CONDITIONS
CL = 15 pF; VCC = 5 V
notes 1 and 2
TYPICAL
HC HCT
15 16
127 62
3.5 3.5
27 27
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V
UNIT
ns
MHz
pF
pF
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
No Preview Available ! |
Philips Semiconductors
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
Product specification
74HC/HCT564
PIN DESCRIPTION
PIN NO.
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12
20
SYMBOL
OE
D0 to D7
GND
CP
Q0 to Q7
VCC
NAME AND FUNCTION
3-state output enable input (active LOW)
data inputs
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
3-state flip-flop outputs
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
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