74HC73 PDF даташит
Спецификация 74HC73 изготовлена «Philips» и имеет функцию, называемую «Dual JK flip-flop with reset negative-edge trigger». |
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Детали детали
Номер произв | 74HC73 |
Описание | Dual JK flip-flop with reset negative-edge trigger |
Производители | Philips |
логотип |
21 Pages
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74HC73
Dual JK flip-flop with reset; negative-edge trigger
Rev. 03 — 12 November 2004
Product data sheet
1. General description
The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power
Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC
standard no. 7A.
The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock
(nCP) and reset (nR) inputs; also complementary nQ and nQ outputs.
The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock
transition for predictable operation.
The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock
and data inputs, forcing the nQ output LOW and the nQ output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features
s Low-power dissipation
s Complies with JEDEC standard no. 7A
s ESD protection:
x HBM EIA/JESD22-A114-B exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V.
s Multiple package options
s Specified from −40 °C to +80 °C and from −40 °C to +125 °C.
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Symbol Parameter
Conditions
Min
tPHL, tPLH
propagation delay
nCP to nQ
CL = 15 pF; VCC = 5 V
-
-
nCP to nQ
-
nR to nQ, nQ
-
fmax maximum clock
frequency
CL = 15 pF; VCC = 5 V
-
CI input capacitance
-
CPD
power dissipation
VI = GND to VCC
[1] -
capacitance per flip-flop
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC2 × fo) = sum of outputs.
Typ
16
16
15
77
3.5
30
4. Ordering information
Max Unit
-
- ns
- ns
- ns
- MHz
- pF
- pF
Table 2: Ordering information
Type number Package
Temperature range Name Description
Version
74HC73N
−40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil)
SOT27-1
74HC73D
−40 °C to +125 °C SO14
plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HC73DB
−40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width SOT337-1
5.3 mm
74HC73PW
−40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
SOT402-1
9397 750 13815
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
2 of 21
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Philips Semiconductors
5. Functional diagram
74HC73
Dual JK flip-flop with reset; negative-edge trigger
14 1J
1 1CP
J Q 1Q 12
FF1
CP
3 1K
2 1R
K Q 1Q 13
R
Fig 1. Functional diagram
7 2J
5 2CP
J Q 2Q 9
FF2
CP
10 2K
6 2R
K Q 2Q 8
R
001aab981
14 1J
7 2J
1 1CP
5 2CP
J
FF
CP
Q 1Q 12
2Q 9
3 1K K
10 2K
Q 1Q 13
2Q 8
R
1R 2R
26
001aab979
Fig 2. Logic symbol
4 1J
1 C1
3 1K
2R
12
13
7 1J
5 C1
10 1K
6R
9
8
001aab980
Fig 3. IEC logic symbol
9397 750 13815
Product data sheet
Rev. 03 — 12 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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