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PDF HFA3824 Data sheet ( Hoja de datos )
| Número de pieza | HFA3824 | |
| Descripción | Direct Sequence Spread Spectrum Baseband Processor | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Direct Sequence Spread
Spectrum Baseband
Processor
The Intersil HFA3824 Direct Sequence
(DSSS) baseband processor is part of the PRISM™
2.4GHz radio chipset, and contains all the functions neces-
sary for a full or half duplex packet baseband transceiver.
The HFA3824 has on-board ADC’s for analog I and Q
inputs, for which the HFA3724/6 IF QMODEM is recom-
mended. Differential phase shift keying modulation schemes
DBPSK and DQPSK, with optional data scrambling capabil-
ity, are combined with a programmable PN sequence of up
to 16 bits. Built-in flexibility allows the HFA3824 to be config-
ured through a general purpose control bus, for a wide range
of applications. A Receive Signal Strength Indicator (RSSI)
monitoring function with on-board 6-bit 2 MSPS ADC pro-
vides Clear Channel Assessment (CCA) to avoid data colli-
sions and optimize network throughput. The HFA3824 is
housed in a thin plastic quad flat package (TQFP) suitable
for PCMCIA board applications.
Ordering Information
PART NO.
HFA3824IV
HFA3824IV96
TEMP.
RANGE (oC)
-40 to 85
-40 to 85
PKG. TYPE PKG. NO.
48 Ld TQFP
Q48.7x7
Tape and Reel
Pinout
HFA3824 (TQFP)
HFA3824
June 1998
File Number 4308.1
Features
• Complete DSSS Baseband Processor
• High Data Rate . . . . . . . . . . . . . . . . . . . . . . up to 4 MBPS
• Processing Gain . . . . . . . . . . . . . . . . . . . . . . . . up to 12dB
• Programmable PN Code . . . . . . . . . . . . . . . up to 16 Bits
• Ultra Small Package . . . . . . . . . . . . . . . . . . . . 7 x 7 x 1mm
• Single Supply Operation (33MHz Max) . . . . . 2.7V to 5.5V
• Single Supply Operation (44MHz Max) . . . . . 3.3V to 5.0V
• Modulation Method. . . . . . . . . . . . . . . .DBPSK or DQPSK
• Supports Full or Half Duplex Operations
• On-Chip A/D Converters for I/Q Data (3-Bit, 44 MSPS)
and RSSI (6-Bit, 2 MSPS)
• Backward Compatible with HSP3824
Applications
• Systems Targeting IEEE802.11 Standard
• DSSS PCMCIA Wireless Transceiver
• Spread Spectrum WLAN RF Modems
• TDMA Packet Protocol Radios
• Part 15 Compliant Radio Links
• Portable Bar Code Scanners/POS Terminal
• Portable PDA/Notebook Computer
• Wireless Digital Audio
• Wireless Digital Video
• PCN/Wireless PBX
Simplified Block Diagram
TEST_CK
TX_PE
TXD
TXCLK
TX_RDY
GND
VDD
R/W
CS
VDDA
GND
IIN
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
RXCLK
RXD
MD_RDY
RX_PE
CCA
GND
MCLK
VDD
RESET
ANTSEL
A/D_CAL
SD
IIN
3-BIT
A/D
QIN
3-BIT
A/D
RSSI
6-BIT
A/D
IOUT
QOUT
DPSK
DEMOD.
CCA
PRO-
CESSOR
INTER-
FACE
CTRL
DPSK
MOD.
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
PRISM and Design™ is a registered trademark of Intersil Corporation. PRISM™ is a trademark of Intersil Corporation.
1 page  
HFA3824
Pin Description (Continued)
NAME
MD_RDY
PIN TYPE I/O
34 O
RX_PE
ANTSEL
SD
33
27
25
I
O
I/O
SCLK
24
I
AS 23
I
R/W 8
I
CS 9
I
TEST 0-7
37, 38, 39,
40, 43, 44,
45, 46
TEST_CK
1
RESET
28
I/O
O
I
MCLK
30
I
IOUT
48
O
QOUT
47
O
NOTE: Total of 48 pins; ALL pins are used.
DESCRIPTION
MD_RDY is an output signal to the network processor, indicating a data packet is ready to be
transferred to the processor. MD_RDY is an active high signal and it envelopes the data trans-
fer over the RXD serial bus. MD_RDY returns to its inactive state when there is no more re-
ceiver data, when the programmable data length counter reaches its value or when the link
has been interrupted. MD_RDY remains inactive during preamble synchronization.
When active, receiver is configured to be operational, otherwise receiver is in standby mode.
This is an active high input signal. In standby, all A/D converters are disabled.
The antenna select signal changes state as the receiver switches from antenna to antenna
during the acquisition process in the antenna diversity mode.
SD is a serial bi-directional data bus which is used to transfer address and data to/from the
internal registers. The bit ordering of an 8-bit word is MSB first. The first 8 bits during transfers
indicate the register address immediately followed by 8 more bits representing the data that
needs to be written or read at that register.
SCLK is the clock for the SD serial bus.The data on SD is clocked at the rising edge. SCLK is
an input clock and it is asynchronous to the internal master clock (MCLK)The maximum rate
of this clock is 11MHz or one half the master clock frequency, whichever is lower.
AS is an address strobe used to envelope the Address or the data on SD.
Logic 1 = envelopes the address bits.
Logic 0 = envelopes the data bits.
R/W is an input to the HFA3824 used to change the direction of the SD bus when reading or
writing data on the SD bus. R/W must be set up prior to the rising edge of SCLK. A high level
indicates read while a low level is a write.
CS is a Chip select for the device to activate the serial control port.The CS doesn’t impact any
of the other interface ports and signals, i.e. the TX or RX ports and interface signals. This is
an active low signal. When inactive SD, SCLK, AS and R/W become “don’t care” signals.
This is a data port that can be programmed to bring out internal signals or data for monitoring.
These bits are primarily reserved by the manufacturer for testing. A further description of the
test port is given at the appropriate section of this data sheet. The direction of these pins are
not established until programming of test registers is complete.
This is the clock that is used in conjunction with the data that is being output from the test bus
(TEST 0-7).
Master reset for device. When active TX and RX functions are disabled. If RESET is kept low
the HFA3824 goes into the power standby mode. RESET does not alter any of the configura-
tion register values nor it presets any of the registers into default values. Device requires pro-
gramming upon power-up.
Master Clock for device. The maximum frequency of this clock is 44MHz. This is used inter-
nally to generate all other internal necessary clocks and is divided by 1, 2, 4, or 8 for the trans-
ceiver clocks.
TX Spread baseband I digital output data. Data is output at the programmed chip rate.
TX Spread baseband Q digital output data. Data is output at the programmed chip rate.
4-5
5 Page 
HFA3824
RX Port
The timing diagram Figure 7 illustrates the relationships
between the various signals of the RX port. The receive data
port serially outputs the demodulated data from RXD. The
data is output as soon as it is demodulated by the HFA3824.
RX_PE must be at its active state throughout the receive
operation. When RX_PE is inactive the device's receive
functions, including acquisition, will be in a stand by mode.
RXCLK is an output from the HFA3824 and is the clock for
the serial demodulated data on RXD. MD_RDY is an output
from the HFA3824 and it envelopes the valid data on RXD.
The HFA3824 can be also programmed to ignore error
detections during the CCITT - CRC 16 check of the header
fields. If programmed to ignore errors the device continues
to output the demodulated data in its entirety regardless of
the CCITT - CRC 16 check result. This option is pro-
grammed through CR 2, bit 5.
Note that RXCLK becomes active after acquisition, well
before valid data begins to appear on RXD and MD_RDY is
asserted. MD_RDY returns to its inactive state under the fol-
lowing conditions:
• The number of data symbols, as defined by the length
field in the protocol, has been received and output
through RXD in its entirety (normal condition).
• PN tracking is lost during demodulation.
• RX_PE is deactivated by the external controller.
MD_RDY and RXCLK can be configured through CR 9, bit
6-7 to be active low, or active high. Energy Detect (ED) pin
45 (Test port), and Carrier Sense (CRS) pin 46 (Test port),
are available outputs from the HFA3824 and can be useful
signals for an effective RX interface design. Use of these
signals is optional. CRS and ED are further described within
this document. The receive port is completely independent
from the operation of the other interface ports including the
TX port, supporting therefore a full duplex mode.
I/Q ADC Interface
The PRISM baseband processor chip (HFA3824) includes
two 3-bit Analog to Digital converters (ADCs) that sample the
analog input from the IF down converter. The I/Q ADC clock,
MCLK, samples at twice the chip rate. The maximum sam-
pling rate is 44MHz (power supply: 3.3V to 5.0V) or 33MHz
(power supply 2.7V to 5.5V).
The interface specifications for the I and Q ADCs are listed
in Table 2.
TABLE 2. I, Q, ADC SPECIFICATIONS
PARAMETER
MIN TYP MAX
Full Scale Input Voltage (VP-P)
Input Bandwidth (-0.5dB)
0.25 0.50
- 20MHz
1.0
-
Input Capacitance (pF)
-5-
Input Impedance (DC)
5kΩ -
-
FS (Sampling Frequency)
- - 44MHz
The voltages applied to pin 16,VREFP and pin 17, VREFN set
the references for the internal I and Q ADC converters. In
addition, VREFP is also used to set the RSSI ADC converter
reference. For a nominal 500mVP-P , the suggested VREFP
voltage is 1.75V, and the suggested VREFN is 0.93V. VREFN
should never be less than 0.25V. Since these ADCs are
intended to sample AC voltages, their inputs are biased
internally and they should be capacitively coupled.
The ADC section includes a compensation (calibration) cir-
cuit that automatically adjusts for temperature and compo-
nent variations of the RF and IF strips. The variations in gain
of limiters, AGC circuits, filters etc. can be compensated for
up to ±4dB. Without the compensation circuit, the ADCs
could see a loss of up to 1.5 bits of the 3 bits of quantization.
The ADC calibration circuit adjusts the ADC reference volt-
ages to maintain optimum quantization of the IF input over
this variation range. It works on the principle of setting the
reference to insure that the signal is at full scale (saturation)
a certain percentage of the time. Note that this is not an AGC
and it will compensate only for slow variations in signal lev-
els (several seconds).
RXCLK
RX_PE
CRS (TEST 7)
MD_RDY
PROCESSING
PREAMBLE/HEADER
RXD
NOTE: MD_RDY active after CRC16.
LSB
DATA
FIGURE 7. RX PORT TIMING
MSB
4-11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HFA3824.PDF ] | |
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